74AHC157; 74AHCT157
Quad 2-input multiplexer
Rev. 02 — 9 November 2007
Product data sheet
1. General description
The 74AHC/AHCT157 are high-speed Si-gate CMOS devices and are pin compatible with
Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74AHC/AHCT157 are quad 2-input multiplexer which select 4 bits of data from two
sources under the control of a common data select input (S). The enable input (E) is
active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of
all other input conditions.
Moving the data from two groups of registers to four common output buses is a common
use of the 74AHC/AHCT157. The state of the common data select input (S) determines
the particular register from which the data comes. It can also be used as function
generator. The device is useful for implementing highly irregular logic by generating any
four of the 16 different functions of two variables with one variable common. The
74AHC/AHCT157 is logic implementation of a 4-pole, 2-position switch, where the
position of the switch is determine by the logic levels applied to S.
The logic equations are:
1Y = E
×
(1I1
×
S + 1I0
×
S)
2Y = E
×
(2I1
×
S + 2I0
×
S)
3Y = E
×
(3I1
×
S + 3I0
×
S)
4Y = E
×
(4I1
×
S + 4I0
×
S)
The 74AHC/AHCT157 is identical to the 74AHC/AHCT158 but has non-inverting (true)
outputs.
2. Features
s
s
s
s
s
s
s
s
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than V
CC
Multiple input enable for easy expansion
Ideal for memory chip select decoding
For 74AHC157 only: operates with CMOS input levels
For 74AHCT157 only: operates with TTL input levels
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A115-A exceeds 200 V
x
CDM JESD22-C101C exceeds 1000 V
NXP Semiconductors
74AHC157; 74AHCT157
Quad 2-input multiplexer
s
Multiple package options
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC157D
74AHCT157D
74AHC157PW
74AHCT157PW
74AHC157BQ
74AHCT157BQ
−40 °C
to +125
°C
DHVQFN16
−40 °C
to +125
°C
TSSOP16
−40 °C
to +125
°C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
SOT763-1
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5
×
3.5
×
0.85 mm
4. Functional diagram
S
E
1I1
1Y
1I0
2I1
2Y
2I0
2
3Y
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1
3I0
1
15
4I1
4Y
4I0
mna484
3I1
3
5
6
11
10
14
13
S
E
1Y
4
2Y
7
3Y
9
4Y
12
mna481
Fig 1. Logic diagram
Fig 2. logic symbol
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
2 of 16
NXP Semiconductors
74AHC157; 74AHCT157
Quad 2-input multiplexer
1
2
3
5
6
11
10
14
13
1I0
1I1
2I0
2Y
2I1
3I0
3I1
4I0
4I1
4Y 12
SELECTOR
MULTIPLEXER
OUTPUTS
7
1Y
4
15
G1
EN
2
3
1
1
MUX
4
3Y
9
5
6
11
10
14
7
9
S
1
E
15
mna483
13
mna482
12
Fig 3. Logic symbol
Fig 4. IEC logic symbol
5. Pinning information
5.1 Pinning
terminal 1
index area
1I0
16 V
CC
15 E
14 4I0
13 4I1
12 4Y
11 3I0
10 3I1
9
001aah066
74AHC157
74AHCT157
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
GND
3Y
9
16 V
CC
15 E
14 4I0
13 4I1
12 4Y
11 3I0
10 3I1
1I1
1Y
2I0
2I1
2Y
GND
(1)
1
S
157
3Y
001aac931
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration SO16, TSSOP16
Fig 6. Pin configuration DHVQFN16
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
3 of 16
NXP Semiconductors
74AHC157; 74AHCT157
Quad 2-input multiplexer
5.2 Pin description
Table 2.
Symbol
S
1I0 to 4I0
1I1 to 4I1
1Y to 4Y
GND
E
V
CC
Pin description
Pin
1
2, 5, 11, 14
3, 6, 10, 13
4, 7, 9, 12
8
15
16
Description
common data select input
data inputs from source 0
data inputs from source 1
multiplexer outputs
ground (0 V)
enable input (active LOW)
supply voltage
6. Functional description
Table 3.
Input
E
H
L
L
L
L
[1]
Function table
[1]
Output
S
X
L
L
H
H
nI0
X
L
H
X
X
nI1
X
X
X
L
H
nY
L
L
H
L
H
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
4 of 16
NXP Semiconductors
74AHC157; 74AHCT157
Quad 2-input multiplexer
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO16 package
TSSOP16 package
DHVQFN16 package
[1]
[2]
[3]
[4]
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
±20
±25
75
-
+150
500
500
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
mW
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
-
-
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
-
-
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
Conditions
Min
2.0
0
0
−40
-
-
74AHC157
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
Min
4.5
0
0
−40
-
-
74AHCT157
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
-
20
V
V
V
°C
ns/V
ns/V
Unit
74AHC_AHCT157_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 9 November 2007
5 of 16
分立器件
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