Smart High-Side Power Switch
BTS716GB
6PDUW +LJK6LGH 3RZHU 6ZLWFK
)RXU &KDQQHOV [ PΩ
6WDWXV )HHGEDFN
Product Summary
2SHUDWLQJ 9ROWDJH
9
EE
$FWLYH FKDQQHOV
2QVWDWH 5HVLVWDQFH
5
21
1RPLQDO ORDG FXUUHQW
,
&XUUHQW OLPLWDWLRQ
,
9
RQH
IRXU SDUDOOHO
PΩ
PΩ
$
$
$
$
Package
P-DSO-20
*HQHUDO 'HVFULSWLRQ
•
•
PG-DSO20
1 FKDQQHO YHUWLFDO SRZHU 026)(7 ZLWK FKDUJH SXPS JURXQG UHIHUHQFHG &026 FRPSDWLEOH LQSXW DQG
GLDJQRVWLF IHHGEDFN PRQROLWKLFDOO\ LQWHJUDWHG LQ 6PDUW 6,3026 WHFKQRORJ\
)XOO\ SURWHFWHG E\ HPEHGGHG SURWHFWLRQ IXQFWLRQV
$SSOLFDWLRQV
•
•
•
•
& FRPSDWLEOH KLJKVLGH SRZHU VZLWFK ZLWK GLDJQRVWLF IHHGEDFN IRU 9 DQG 9 JURXQGHG ORDGV
$OO W\SHV RI UHVLVWLYH LQGXFWLYH DQG FDSDFLWYH ORDGV
0RVW VXLWDEOH IRU ORDGV ZLWK KLJK LQUXVK FXUUHQWV VR DV ODPSV
5HSODFHV HOHFWURPHFKDQLFDO UHOD\V IXVHV DQG GLVFUHWH FLUFXLWV
%DVLF )XQFWLRQV
•
•
•
•
•
•
•
9HU\ ORZ VWDQGE\ FXUUHQW
&026 FRPSDWLEOH LQSXW
,PSURYHG HOHFWURPDJQHWLF FRPSDWLELOLW\ (0&
)DVW GHPDJQHWL]DWLRQ RI LQGXFWLYH ORDGV
6WDEOH EHKDYLRXU DW XQGHUYROWDJH
:LGH RSHUDWLQJ YROWDJH UDQJH
/RJLF JURXQG LQGHSHQGHQW IURP ORDG JURXQG
3URWHFWLRQ )XQFWLRQV
•
•
•
•
•
•
•
•
Block Diagram
9EE
,1
67
,1
/RJLF
&KDQQHO
&KDQQHO
6KRUW FLUFXLW SURWHFWLRQ
2YHUORDG SURWHFWLRQ
&XUUHQW OLPLWDWLRQ
7KHUPDO VKXWGRZQ
2YHUYROWDJH SURWHFWLRQ LQFOXGLQJ ORDG GXPS
ZLWK H[WHUQDO
UHVLVWRU
5HYHUVH EDWWHU\ SURWHFWLRQ ZLWK H[WHUQDO UHVLVWRU
/RVV RI JURXQG DQG ORVV RI 9
EE
SURWHFWLRQ
(OHFWURVWDWLF GLVFKDUJH SURWHFWLRQ (6'
/RDG
/RDG
'LDJQRVWLF )XQFWLRQ
•
•
•
,1
67
,1
/RJLF
&KDQQHO
&KDQQHO
/RDG
'LDJQRVWLF IHHGEDFN ZLWK RSHQ GUDLQ RXWSXW
2SHQ ORDG GHWHFWLRQ LQ 2))VWDWH
)HHGEDFN RI WKHUPDO VKXWGRZQ LQ 21VWDWH
*1'
/RDG
Data Sheet
1
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS716GB
)XQFWLRQDO GLDJUDP
RYHUYROWDJH
SURWHFWLRQ
LQWHUQDO
YROWDJH VXSSO\
,1
ORJLF
JDWH
FRQWURO
FKDUJH
SXPS
WHPSHUDWXUH
VHQVRU
2SHQ ORDG
GHWHFWLRQ
FXUUHQW OLPLW
9%%
FODPS IRU
LQGXFWLYH ORDG
287
(6'
UHYHUVH
EDWWHU\
SURWHFWLRQ
/2$'
67
FKDQQHO
,1
control and protection circuit
of
channel 2
287
*1'
,1
control and protection circuit
of
channel 3
287
67
IN4
control and protection circuit
of
channel 4
287
*1'
Data Sheet
2
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS716GB
Pin Definitions and Functions
Pin
1,10,
11,12,
15,16,
19,20
3
5
7
9
18
17
14
13
4
8
2
6
Symbol Function
V
bb
Positive power supply voltage.
Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 2 and also for low
thermal resistance
IN1
Input 1,2,3,4
activates channel 1,2,3,4 in case
of logic high signal
IN2
IN3
IN4
OUT1
Output 1,2,3,4
protected high-side power output
of channel 1,2,3,4. Design the wiring for the
OUT2
max. short circuit current
OUT3
OUT4
ST1/2
Diagnostic feedback 1/2,3/4
of channel 1,2,3,4
ST3/4
open drain, low on failure
GND1/2
Ground
of chip 1 (channel 1,2)
GND3/4
Ground
of chip 2 (channel 3,4)
Pin configuration
(top view)
V
bb
GND1/2
IN1
ST1/2
IN2
GND3/4
IN3
ST3/4
IN4
V
bb
1
2
3
4
5
6
7
8
9
10
•
20
19
18
17
16
15
14
13
12
11
V
bb
V
bb
OUT1
OUT2
V
bb
V
bb
OUT3
OUT4
V
bb
V
bb
Data Sheet
3
V1.0, 2007-05-13
Smart High-Side Power Switch
BTS716GB
Parameter
Supply voltage (overvoltage protection see page 6)
Supply voltage for full short circuit protection
T
j,start
= -40 ...+150°C
Load current (Short-circuit current, see page 6)
Load dump protection
2
)
V
LoadDump
=
V
A
+
V
s
,
V
A
= 13.5 V
R
I
3
)
= 2
Ω,
t
d
= 400 ms; IN = low or high,
each channel loaded with
R
L
= 13.5
Ω,
Operating temperature range
Storage temperature range
Power dissipation (DC)
5)
T
a
= 25°C:
(all channels active)
T
a
= 85°C:
Maximal switchable inductance, single pulse
V
bb
= 12V,
T
j,start
= 150°C
5)
,
see diagrams on page 10
I
L
= 2.3 A,
E
AS
= 76 mJ, 0
Ω
one channel:
I
L
= 3.3 A,
E
AS
= 182 mJ, 0
Ω
two parallel channels:
I
L
= 4.7 A,
E
AS
= 460 mJ, 0
Ω
four parallel channels:
Electrostatic discharge capability (ESD)
IN:
(Human Body Model)
ST:
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5kΩ; C=100pF
Symbol
Values
43
36
Unit
V
V
A
V
°C
W
V
bb
V
bb
I
L
V
Load dump4
)
T
j
T
stg
P
tot
I
L(lim)
1
60
-40 ...+150
-55 ...+150
3.6
1.9
Z
L
21
25
30
1.0
4.0
8.0
-10 ... +16
±0.3
±5.0
±5.0
mH
V
ESD
kV
Input voltage (DC)
see internal circuit diagram page 9
Current through input pin (DC)
Pulsed current through input pin
6
)
Current through status pin (DC)
V
IN
I
IN
I
IN
I
ST
V
mA
1)
2
)
3)
4)
5
)
6
)
Operation in current limitation is considered as "outside" normal operating range. Protection functions are not
designed for continuous repetitive operation.
Supply voltages higher than V
bb(AZ)
require an external current limit for the GND and status pins (a 150Ω
resistor for the GND connection is recommended.
R
I
= internal resistance of the load dump test pulse generator
V
Load dump
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
only for testing
4
V1.0, 2007-05-13
Data Sheet
Smart High-Side Power Switch
BTS716GB
Parameter and Conditions
Thermal resistance
junction - soldering point
7)8)
junction – ambient
6)
@ 6 cm
2
cooling area
Symbol
Values
min
typ
max
--
--
--
--
--
--
44
35
17
--
--
--
Unit
each channel:
R
thjs
R
thja
one channel active:
all channels active:
K/W
Electrical Characteristics
Parameter and Conditions,
each of the four channels
at T
j
= -40...+150°C,
V
bb
= 12 V unless otherwise specified
Symbol
Values
min
typ
max
Unit
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT);
IL = 2 A
each channel,
T
j
= 25°C:
R
ON
T
j
= 150°C:
two parallel channels,
T
j
= 25°C:
four parallel channels,
T
j
= 25°C:
see diagram, page 11
--
--
--
--
2.3
3.3
4.7
--
110
210
55
28
2.6
3.7
5.3
--
140
280
70
35
--
--
--
2
mΩ
Nominal load current
one channel active:
I
L(NOM)
two parallel channels active:
four parallel channels active:
A
Device on PCB
6)
,
Ta
=
85°C,
Tj
≤
150°C
Output current
while GND disconnected or pulled up;
Vbb = 32 V,
VIN
= 0,
see diagram page 9; (not tested specified by design)
Turn-on time
9
)
IN
to 90%
I
L(GNDhigh)
mA
µs
Turn-off time
R
L
= 12
Ω
Slew rate on
8
)
Slew rate off
8
)
IN
V
OUT
:
t
on
to 10%
V
OUT
:
t
off
--
--
0.2
0.2
100
100
--
--
250
270
1.0
1.1
10 to 30%
V
OUT
,
R
L
= 12
Ω:
dV/dt
on
70 to 40%
V
OUT
,
R
L
= 12
Ω:
-dV/dt
off
V/µs
V/µs
7
)
8
)
9
)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
Soldering point: upper side of solder edge of device pin 15. See page 14
See timing diagram on page 12.
5
V1.0, 2007-05-13
Data Sheet
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
