74F574 Octal D-Type Flip-Flop with 3-STATE Outputs
April 1988
Revised October 2000
74F574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The 74F574 is a high-speed, low power octal flip-flop with a
buffered common Clock (CP) and a buffered common
Output Enable (OE). The information presented to the D
inputs is stored in the flip-flops on the LOW-to-HIGH Clock
(CP) transition.
This device is functionally identical to the 74F374 except
for the pinouts.
Features
s
Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
s
Useful as input or output port for microprocessors
s
Functionally identical to 74F374
s
3-STATE outputs for bus-oriented applications
Ordering Code:
Order Number
74F574SC
74F574SJ
74F574PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009567
www.fairchildsemi.com
74F574
Unit Loading/Fan Out
Pin Names
D
0
–D
7
CP
OE
O
0
–O
7
Data Inputs
Clock Pulse Input (Active LOW)
3-STATE Output Enable Input (Active LOW)
3-STATE Outputs
Description
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
150/40 (33.3)
−
3 mA/24 mA (20 mA)
Functional Description
The 74F574 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Function Table
Inputs
OE
H
H
H
H
L
L
L
L
CP
H
D
L
H
L
H
L
H
L
H
Internal Outputs
Function
Q
NC
NC
L
H
L
H
NC
NC
O
Z
Z
Z
Z
L
H
NC
NC
Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
H
H
H
Logic Diagram
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
74F574
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCZ
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
55
−60
4.75
3.75
−0.6
50
−50
−150
500
86
10% V
CC
2.5
2.4
2.7
2.7
0.5
5.0
7.0
50
V
µA
µA
µA
V
µA
mA
µA
µA
mA
µA
mA
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0V
Max
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OL
=
24 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
OUT
=
2.7V
V
OUT
=
0.5V
V
OUT
=
0V
V
OUT
=
5.25V
V
O
=
HIGH Z
3
www.fairchildsemi.com
74F574
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Maximum Clock Frequency
Propagation Delay
CP to O
n
Output Enable Time
100
2.5
2.5
3.0
3.0
1.5
1.5
5.3
5.3
5.5
6.0
3.3
2.8
8.5
8.5
9.0
9.0
5.5
5.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
60
2.5
2.5
2.5
2.5
1.5
1.5
9.5
9.5
10.5
10.5
7.0
7.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
70
2.5
2.5
2.5
2.5
1.5
1.5
8.5
8.5
10.0
10.0
6.5
6.5
ns
Max
MHz
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
Set-up Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
CP Pulse Width
HIGH or LOW
2.5
2.0
2.0
2.0
5.0
5.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
Min
3.0
2.5
2.0
2.0
5.0
5.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
2.5
2.0
2.0
2.0
5.0
5.0
ns
ns
Max
Units
www.fairchildsemi.com
4
74F574
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
www.fairchildsemi.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
