MC74HC14A
Hex Schmitt-Trigger
Inverter
High−Performance Silicon−Gate CMOS
The MC74HC14A is identical in pinout to the LS14, LS04 and the
HC04. The device inputs are compatible with Standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
The HC14A is useful to “square up” slow input rise and fall times.
Due to hysteresis voltage of the Schmitt trigger, the HC14A finds
applications in noisy environments.
Features
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SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 60 FETs or 15 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
LOGIC DIAGRAM
A1
1
2
Y1
1
Y2
14
PIN ASSIGNMENT
V
CC
14
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
1
A1
2
Y1
3
A2
4
Y2
5
A3
6
Y3
7
GND
14−Lead
(Top View)
MARKING DIAGRAMS
14
HC14AG
AWLYWW
1
SOIC−14 NB
A
L, WL
Y, YY
W, WW
G or
G
TSSOP−14
HC
14A
ALYWG
G
A2
3
4
A3
5
6
Y3
Y=A
A4
9
8
Y4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Pin 14 = V
CC
Pin 7 = GND
(Note: Microdot may be in either location)
A5
11
10
Y5
FUNCTION TABLE
Inputs
Outputs
Y
H
L
A6
13
12
Y6
A
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 14
Publication Order Number:
MC74HC14A/D
MC74HC14A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
T
stg
T
L
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
SOIC Package†
TSSOP Package†
Value
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±20
±25
±50
500
450
–65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance
circuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
–55
0
0
0
Max
6.0
V
CC
+125
No Limit*
No Limit*
No Limit*
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*When V
in
= 50% V
CC
, I
CC
> 1mA
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2
MC74HC14A
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
T+
max
Parameter
Maximum Positive−Going Input
Threshold Voltage
(Figure 3)
Minimum Positive−Going Input
Threshold Voltage
(Figure 3)
Maximum Negative−Going Input
Threshold Voltage
(Figure 3)
Minimum Negative−Going Input
Threshold Voltage
(Figure 3)
Maximum Hysteresis Voltage
(Figure 3)
Condition
V
out
= 0.1V
|I
out
|
≤
20mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
−55 to 25°C
1.50
2.15
3.15
4.20
1.0
1.5
2.3
3.0
0.9
1.4
2.0
2.6
0.3
0.5
0.9
1.2
1.20
1.65
2.25
3.00
0.20
0.25
0.40
0.50
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
1.0
≤85°C
1.50
2.15
3.15
4.20
0.95
1.45
2.25
2.95
0.95
1.45
2.05
2.65
0.3
0.5
0.9
1.2
1.20
1.65
2.25
3.00
0.20
0.25
0.40
0.50
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
10
≤125°C
1.50
2.15
3.15
4.20
0.95
1.45
2.25
2.95
0.95
1.45
2.05
2.65
0.3
0.5
0.9
1.2
1.20
1.65
2.25
3.00
0.20
0.25
0.40
0.50
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
±1.0
40
mA
mA
V
Unit
V
V
T+
min
V
out
= 0.1V
|I
out
|
≤
20mA
V
V
T−
max
V
out
= V
CC
− 0.1V
|I
out
|
≤
20mA
V
V
T−
min
V
out
= V
CC
− 0.1V
|I
out
|
≤
20mA
V
V
H
max
(Note 1)
V
out
= 0.1V or V
CC
− 0.1V
|I
out
|
≤
20mA
V
V
H
min
(Note 1)
Minimum Hysteresis Voltage
(Figure 3)
V
out
= 0.1V or V
CC
− 0.1V
|I
out
|
≤
20mA
V
V
OH
Minimum High−Level Output
Voltage
V
in
≤
V
T−
min
|I
out
|
≤
20mA
V
in
≤
V
T−
min
V
V
OL
Maximum Low−Level Output
Voltage
V
in
≥
V
T+
max
|I
out
|
≤
20mA
V
in
≥
V
T+
max
I
in
I
CC
Maximum Input Leakage
Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0mA
1. V
H
min > (V
T+
min) − (V
T−
max); V
H
max = (V
T+
max) − (V
T−
min).
AC CHARACTERISTICS
(C
L
= 50pF, Input t
r
= t
f
= 6ns)
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
−55 to 25°C
75
30
15
13
75
27
15
13
10
≤85°C
95
40
19
16
95
32
19
16
10
≤125°C
110
55
22
19
110
36
22
19
10
Unit
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
ns
C
in
Maximum Input Capacitance
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Inverter)*
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
22
pF
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3
MC74HC14A
t
f
90%
INPUT A
50%
10%
t
PLH
90%
OUTPUT Y
50%
10%
t
TLH
t
r
V
CC
GND
t
PHL
t
THL
Figure 1. Switching Waveforms
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
VT , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS)
4
3
(V
T+
)
V
H
typ
2
(V
T-
)
1
2
3
4
5
V
CC
, POWER SUPPLY VOLTAGE (VOLTS)
V
H
typ = (V
T+
typ) - (V
T-
typ)
6
Figure 3. Typical Input Threshold, V
T+
, V
T−
versus Power Supply Voltage
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4
MC74HC14A
A
Y
(a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times
V
H
V
in
V
CC
V
T+
V
T-
GND
V
OH
V
out
V
OL
V
out
V
in
V
H
(b) A Schmitt-Trigger Offers Maximum Noise Immunity
V
CC
V
T+
V
T-
GND
V
OH
V
OL
Figure 4. Typical Schmitt−Trigger Applications
ORDERING INFORMATION
Device
MC74HC14ADG
MC74HC14ADR2G
MC74HC14ADTG
MC74HC14ADTR2G
NLV74HC14ADG*
NLV74HC14ADR2G*
NLV74HC14ADTG*
NLV74HC14ADTR2G*
Package
SOIC−14 NB
(Pb−Free)
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
SOIC−14 NB
(Pb−Free)
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
TSSOP−14
(Pb−Free)
Shipping
†
55 Units / Rail
2500 / Tape & Reel
96 Units / Rail
2500 / Tape & Reel
55 Units / Rail
2500 / Tape & Reel
96 Units / Rail
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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