74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 5 — 26 February 2016
Product data sheet
1. General description
The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device
features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of
their corresponding Dn inputs that meet the set-up and hold time requirements on the
LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently
of clock and data inputs. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Input levels:
For 74HC273: CMOS level
For 74HCT273: TTL level
Common clock and master reset
Eight positive edge-triggered D-type flip-flops
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC273D
74HCT273D
74HC273DB
74HCT273DB
74HC273PW
74HCT273PW
74HC273BQ
74HCT273BQ
40 C
to +125
C
40 C
to +125
C
TSSOP20
40 C
to +125
C
SSOP20
plastic shrink small outline package; 20 leads; body width
5.3 mm
plastic thin shrink small outline package; 20 leads; body
width 4.4 mm
SOT339-1
SOT360-1
SOT764-1
40 C
to +125
C
SO20
Description
Version
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Type number
DHVQFN20 plastic dual in-line compatible thermal enhanced very thin
quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
Nexperia
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT273
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 26 February 2016
2 of 20
Nexperia
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
Fig 4.
Logic diagram
74HC_HCT273
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 26 February 2016
3 of 20
Nexperia
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO20, SSOP20 and
TSSOP20
Fig 6.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
MR
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
D0, D1, D2, D3, D4, D5, D6, D7
GND
CP
V
CC
Pin description
Pin
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
Description
master reset input (active LOW)
flip-flop output
data input
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
supply voltage
74HC_HCT273
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 26 February 2016
4 of 20
Nexperia
74HC273; 74HCT273
Octal D-type flip-flop with reset; positive-edge trigger
6. Functional description
Table 3.
Function table
[1]
Inputs
MR
reset (clear)
load “1”
load “0”
[1]
Operating modes
Outputs
CP
X
Dn
X
h
l
Qn
L
H
L
L
H
H
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO20, SSOP20, TSSOP20 and
DHVQFN20 package
[1]
[2]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
Max
+7
20
20
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO20 package: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN20 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
74HC_HCT273
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 26 February 2016
5 of 20
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