74FST6800
10−Bit Bus Switch with
Precharged Outputs
The ON Semiconductor 74FST6800 is a 10−bit bus switch with
precharged outputs. The device is CMOS TTL compatible when
operating between 4.0 and 5.5 Volts. The device exhibits extremely
low R
ON
and adds nearly zero propagation delay. The device adds no
noise or ground bounce to the system.
Features
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•
•
•
•
•
•
•
•
R
ON
t
4
W
Typical
Less Than 0.25 ns−Max Delay Through Switch
Nearly Zero Standby Current
No Circuit Bounce
Control Inputs are TTL/CMOS Compatible
Pin−For−Pin Compatible With QS6800, FST6800, CBT6800
All Popular Packages: SOIC−24, TSSOP−24, QSOP−24
All Devices in Package TSSOP are Inherently Pb−Free*
24
OE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
BIASV
MARKING
DIAGRAMS
24
24
1
SOIC−24
DW SUFFIX
CASE 751E
1
FST6800
AWLYWW
24
FST
6800
ALYW
1
1
TSSOP−24
DT SUFFIX
CASE 948H
24
1
QSOP−24
QS SUFFIX
CASE 492B
24
FST6800
AWLYYWW
1
Figure 1. 24−Lead Pinout
TRUTH TABLE
OE
L
H
B
0
−B
9
A
0
−A
9
Bias V
Function
Connect
Precharge
A
L, WL
Y, YY
W, WW
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
NOTE:
H = HIGH Voltage Level
L = LOW Voltage Level
PIN NAMES
Pin
OE
A
B
Description
Bus Switch Enable
Bus A
Bus B
ORDERING INFORMATION
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
June, 2006
−
Rev. 6
1
Publication Order Number:
74FST6800/D
74FST6800
13
2
23
Bias V
B
0
A
0
A
9
11
14
B
9
OE
1
Figure 2. Logic Diagram
ORDERING INFORMATION
Device Order Number
74FST6800DW
74FST6800DWR2
74FST6800DT
74FST6800DTR2
74FST6800QS
Package
SOIC−24
SOIC−24
TSSOP−24*
(Pb−Free)
TSSOP−24*
(Pb−Free)
QSOP−24
Shipping
†
48 Units / Rail
2500 Units / Tape & Reel
96 Units / Rail
2500 Units / Tape & Reel
96 Units / Rail
74FST6800QSR
QSOP−24
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
SOIC
TSSOP
QSOP
Oxygen Index: 28 to 34
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
V
I
t
GND
V
O
t
GND
Parameter
Value
*0.5
to
)7.0
*0.5
to
)7.0
*0.5
to
)7.0
*50
*50
128
$100
$100
*65
to
)150
260
)150
125
170
200
Level 1
UL 94 V−0 @ 0.125 in
u2000
u200
N/A
V
Unit
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
MSL
F
R
V
ESD
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
I
Latchup
Latchup Performance
Above V
CC
and Below GND at 85°C (Note 4)
$500
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
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2
74FST6800
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
A
Dt/DV
Supply Voltage
Input Voltage
Output Voltage
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
Switch I/O
Switch Control Input
V
CC
= 5.0 V
$
0.5 V
Parameter
Operating, Data Retention Only
(Note 5)
(HIGH or LOW State)
Min
4.0
0
0
*40
0
Max
5.5
5.5
5.5
)85
DC
5
Unit
V
V
V
°C
ns/V
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IK
V
IH
V
IL
I
I
I
OZ
R
ON
Parameter
Clamp Diode Resistance
High−Level Input Voltage
Low−Level Input Voltage
Input Leakage Current
OFF−STATE Leakage Current
Switch On Resistance (Note 6)
0
v
V
IN
v
5.5 V
0
v
A, B
v
V
CC
V
IN
= 0 V, I
IN
= 64 mA
V
IN
= 0 V, I
IN
= 30 mA
V
IN
= 2.4 V, I
IN
= 15 mA
V
IN
= 2.4 V, I
IN
= 15 mA
I
CC
DI
CC
Quiescent Supply Current
Increase In I
CC
per Input
V
IN
= V
CC
or GND, I
OUT
= 0
One input at 3.4 V, Other inputs at V
CC
or GND
I
IN
=
*18mA
Conditions
V
CC
(V)
4.5
4.0 to 5.5
4.0 to 5.5
5.5
5.5
4.5
4.5
4.5
4.0
5.5
5.5
4
4
8
11
2.0
0.8
$1.0
$1.0
7
7
15
20
3
2.5
mA
mA
T
A
=
*405C
to
)855C
Min
Typ*
Max
*1.2
Unit
V
V
V
mA
mA
W
*Typical values are at V
CC
= 5.0 V and T
A
= 25°C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
T
A
=
*405C
to
)855C
C
L
= 50 pF, RU = RD = 500
W
V
CC
= 4.5−5.5 V
Symbol
t
PHL
,
t
PLH
t
PZH
,
t
PZL
t
PHZ
,
t
PLZ
Parameter
Prop Delay Bus to Bus (Note 7)
Output Enable Time, I
OE
to Bus A, B
Output Disable Time, I
OE
to Bus A, B
Conditions
V
I
= OPEN
Bias V = GND
V
I
= OPEN for t
PZH
Bias V = GND
V
I
= OPEN for t
PHZ
1.0
1.0
Min
Max
0.25
5.1
5.5
V
CC
= 4.0 V
Min
Max
0.25
5.6
5.5
Unit
ns
ns
ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE
(Note 8)
Symbol
C
IN
C
I/O
Parameter
Control Pin Input Capacitance
A/B Port Input/Output Capacitance
Conditions
V
CC
= 5.0 V
V
CC
, OE = 5.0 V
Typ
3
5
Max
Unit
pF
pF
8. T
A
=
)25°C,
f = 1 MHz, Capacitance is characterized but not tested.
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74FST6800
AC Loading and Waveforms
V
I
FROM
OUTPUT
UNDER
TEST
500
W
C
L
*
500
W
NOTES:
1. Input driven by 50
W
source terminated in 50
W.
2. CL includes load and stray capacitance.
*C
L
= 50 pF
Figure 3. AC Test Circuit
t
f
= 2.5 nS
90 %
SWITCH
INPUT
1.5 V
10 %
t
PLH
1.5 V
90 %
1.5 V
t
f
= 2.5 nS
3.0 V
10 %
t
PLH
GND
V
OH
OUTPUT
1.5 V
V
OL
Figure 4. Propagation Delays
t
f
= 2.5 nS
t
f
= 2.5 nS
ENABLE
INPUT
90 %
1.5 V
10 %
t
PZL
OUTPUT
1.5 V
t
PZH
10 %
90 %
1.5 V
GND
t
PZL
3.0 V
V
OL
+ 0.3 V
V
OL
t
PHZL
V
OH
1.5 V
OUTPUT
V
OH
−
0.3 V
Figure 5. Enable/Disable Delays
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74FST6800
PACKAGE DIMENSIONS
SOIC−24
D SUFFIX
CASE 751E−04
ISSUE E
13
−A−
24
−B−
12X
P
0.010 (0.25)
M
B
M
1
12
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
15.25
15.54
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
0.23
0.32
0.13
0.29
0
_
8
_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.601
0.612
0.292
0.299
0.093
0.104
0.014
0.019
0.016
0.035
0.050 BSC
0.009
0.013
0.005
0.011
0
_
8
_
0.395
0.415
0.010
0.029
24X
D
0.010 (0.25)
M
J
T A
S
B
S
F
R
C
−T−
SEATING
PLANE
22X
X 45
_
G
K
M
TSSOP−24
DT SUFFIX
CASE 948H−01
ISSUE A
24X
K
REF
0.10 (0.004)
0.15 (0.006) T U
S
M
T U
S
V
S
2X
L/2
24
13
L
PIN 1
IDENT.
1
12
B
−U−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE −W−.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
7.70
7.90
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
_
8
_
INCHES
MIN
MAX
0.303
0.311
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0
_
8
_
0.15 (0.006) T U
S
A
−V−
C
0.10 (0.004)
−T−
SEATING
PLANE
D
N
G
0.25 (0.010)
M
N
F
DETAIL E
H
K
K1
J1
−W−
SECTION N−N
J
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
DETAIL E
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