MC74HCT244A
Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT244A is identical in pinout to the LS244. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High−Speed CMOS inputs. The HCT244A is an octal
noninverting buffer line driver line receiver designed to be used with
3−state memory address drivers, clock drivers, and other bus−oriented
systems. The device has non−inverted outputs and two active−low
output enables.
The HCT244A is the non−inverting version of the HCT240. See
also HCT241.
Features
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SOIC−20W
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
ENABLE A
A1
YB4
A2
YB3
A3
YB2
A4
YB1
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
ENABLE B
YA1
B4
YA2
B3
YA3
B2
YA4
B1
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1
mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
•
Chip Complexity: 112 FETs or 28 Equivalent Gates
•
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
A1
A2
A3
A4
DATA INPUTS
B1
B2
B3
B4
2
4
6
8
11
13
15
17
18
16
14
12
9
7
5
3
YA1
YA2
YA3
YA4
YB1
YB2
YB3
YB4
MARKING DIAGRAMS
20
HCT244A
AWLYYWWG
1
SOIC−20W
A
WL, L
YY, Y
WW, W
G or
G
1
TSSOP−20
20
HCT
244A
ALYWG
G
NONINVERTING
OUTPUTS
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Enable A,
Enable B
L
L
H
A, B
L
H
X
Outputs
YA, YB
L
H
Z
1
OUTPUT ENABLE A
ENABLES ENABLE B 19
PIN 20 = V
CC
PIN 10 = GND
Z = high impedance, X = don’t care
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
Figure 1. Logic Diagram
©
Semiconductor Components Industries, LLC, 2014
1
September, 2014 − Rev. 14
Publication Order Number:
MC74HCT244A/D
MC74HCT244A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
T
stg
T
L
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
SOIC Package†
TSSOP Package†
Value
–0.5 to +7
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±20
±35
±75
500
450
–65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
_C
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 2)
Min
4.5
0
–55
0
Max
5.5
V
CC
+125
500
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High−Level Input Voltage
Maximum Low−Level Input
Voltage
Minimum High−Level Output
Voltage
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
6 mA
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
6 mA
I
in
I
OZ
I
CC
DI
CC
Maximum Input Leakage Current
Maximum Three−State Leakage
Current
Maximum Quiescent Supply
Current (per Package)
Additional Quiescent Supply
Current
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH;
V
out
= V
CC
or GND
V
in
= V
CC
or GND I
out
= 0
mA
V
in
= 2.4 V, Any One Input
V
in
= V
CC
or GND, Other Inputs
l
out
= 0
mA
V
CC
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
5.5
–55 to
25_C
2
2
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
±0.5
4
≤
85_C
2
2
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
±5.0
40
≤
125_C
2
2
0.8
0.8
4.4
5.4
3.7
0.1
0.1
0.4
±1.0
±10
160
mA
mA
mA
V
Unit
V
V
V
Î
Î
ÎÎÎ
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ Î Î Î Î
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î Î Î
Î
Î
≥
−55_C
2.9
25_C to 125_C
2.4
5.5
mA
1. Total Supply Current = I
CC
+
ΣDI
CC
.
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MC74HCT244A
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0 V
±10%,
C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
t
PLZ
,
t
PHZ
t
PZL
,
t
PZH
t
TLH
,
t
THL
C
in
C
out
Parameter
Maximum Propagation Delay, A to YA or B to YB
(Figures 2 and 4)
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 3 and 5)
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 3 and 5)
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
Maximum Input Capacitance
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
–55 to 25_C
20
26
22
12
10
15
≤
85_C
25
33
28
15
10
15
≤
125_C
30
39
33
18
10
15
Unit
ns
ns
ns
ns
pF
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
55
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
SWITCHING WAVEFORMS
t
r
INPUT
A OR B
t
PLH
OUTPUT
YA OR YB
t
TLH
90%
1.3 V
10%
t
THL
2.7 V
1.3 V
0.3 V
t
PHL
t
f
3V
GND
Figure 2.
3V
ENABLE
A OR B
1.3 V
GND
t
PZL
OUTPUT Y
1.3 V
t
PZH
OUTPUT Y
1.3 V
t
PHZ
10%
90%
t
PLZ
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
Figure 3.
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