74F258A Quad 2-Input Multiplexer with 3-STATE Outputs
April 1988
Revised January 2004
74F258A
Quad 2-Input Multiplexer with 3-STATE Outputs
General Description
The 74F258A is a quad 2-input multiplexer with 3-STATE
outputs. Four bits of data from two sources can be selected
using a common data select input. The four outputs
present the selected data in the complement (inverted)
form. The outputs may be switched to a high impedance
state with a HIGH on the common Output Enable (OE)
input, allowing the outputs to interface directly with bus-ori-
ented systems.
Features
s
Multiplexer expansion by tying outputs together
s
Inverting 3-STATE outputs
Ordering Code:
Order Number
74F258ASC
Package Number
M16A
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Logic Symbols
Connection Diagram
IEEE/IEC
© 2004 Fairchild Semiconductor Corporation
DS009508
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74F258A
Unit Loading/Fan Out
Pin Names
S
OE
I
0a
–I
0d
I
1a
–I
1d
Z
a
–Z
d
Description
Common Data Select Input
3-STATE Output Enable Input (Active LOW)
Data Inputs from Source 0
Data Inputs from Source 1
3-STATE Inverting Data Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
−
3 mA/24 mA (20 mA)
Truth Table
Output
Enable
OE
H
L
L
L
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Functional Description
Data
Output
Inputs
I
0
X
X
X
L
H
I
1
X
L
H
X
X
Z
Z
H
L
H
L
The 74F258A is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a common Select input (S). When the Select
input is LOW, the I
0x
inputs are selected and when Select
is HIGH, the I
1x
inputs are selected. The data on the
selected inputs appears at the outputs in inverted form.
The 74F258A is the logic implementation of a 4-pole, 2-
position switch where the position of the switch is deter-
mined by the logic levels supplied to the Select input. The
logic equation for the outputs is shown below:
Z
n
=
OE • (I
1n
• S
+
I
0n
• S)
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance OFF state. If the outputs of
the 3-STATE devices are tied together, all but one device
must be in the high impedance state to avoid high currents
that would exceed the maximum ratings. Designers should
ensure that Output Enable signals to 3-STATE devices
whose outputs are tied together are designed so there is
no overlap.
Select
Input
S
X
H
H
L
L
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F258A
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCH
I
CCL
I
CCZ
Output LOW Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
6.2
15.1
11.3
−60
4.75
3.75
−0.6
50
−50
−150
500
9.5
23
17
10% V
CC
2.5
2.4
2.7
2.7
0.5
5.0
7.0
50
V
µA
µA
µA
V
µA
mA
µA
µA
mA
µA
mA
mA
mA
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0V
Max
Max
Max
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OL
=
24 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
OUT
=
2.7V
V
OUT
=
0.5V
V
OUT
=
0V
V
OUT
=
V
CC
V
O
=
HIGH
V
O
=
LOW
V
O
=
HIGH Z
3
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74F258A
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Propagation Delay
I
n
to Z
n
Propagation Delay
S to Z
n
Output Enable Time
2.5
1.0
3.0
2.5
2.0
2.5
2.0
2.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
Max
5.3
4.0
7.5
7.0
6.0
7.0
6.0
6.0
T
A
= −5°C
to
+125°C
V
CC
=
5.0V
C
L
=
50 pF
Min
2.0
1.0
3.0
2.5
2.0
2.5
1.5
2.0
Max
7.5
6.0
9.5
9.0
8.0
9.0
7.0
8.5
T
A
=
0°C to
+70°C
V
CC
=
5.0V
C
L
=
50 pF
Min
2.0
1.0
3.0
2.5
2.0
2.5
2.0
2.0
Max
6.0
5.0
8.5
8.0
7.0
8.0
7.0
7.0
ns
ns
ns
Units
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4
74F258A Quad 2-Input Multiplexer with 3-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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