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74LV573N,112: 产品描述IC OCTAL D TRANSP LATCH 20-DIP; 产品类别逻辑逻辑; 文件大小112KB，共18页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com; 标准

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74LV573N,112概述

IC OCTAL D TRANSP LATCH 20-DIP

74LV573N,112规格参数

参数名称	属性值
Brand Name	NXP Semiconductor
是否Rohs认证	符合
厂商名称	NXP(恩智浦)
零件包装代码	DIP
包装说明	DIP, DIP20,.3
针数	20
制造商包装代码	SOT146-1
Reach Compliance Code	compliant
其他特性	BROADSIDE VERSION OF 373
系列	LV/LV-A/LVX/H
JESD-30 代码	R-PDIP-T20
JESD-609代码	e4
长度	26.73 mm
负载电容（CL）	50 pF
逻辑集成电路类型	BUS DRIVER
最大I（ol）	0.008 A
位数	8
功能数量	1
端口数量	2
端子数量	20
最高工作温度	125 °C
最低工作温度	-40 °C
输出特性	3-STATE
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	DIP
封装等效代码	DIP20,.3
封装形状	RECTANGULAR
封装形式	IN-LINE
包装方法	TUBE
峰值回流温度（摄氏度）	260
电源	3.3 V
Prop。Delay @ Nom-Sup	29 ns
传播延迟（tpd）	53 ns
认证状态	Not Qualified
座面最大高度	4.2 mm
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	1 V
标称供电电压 (Vsup)	3.3 V
表面贴装	NO
技术	CMOS
温度等级	AUTOMOTIVE
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	THROUGH-HOLE
端子节距	2.54 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
宽度	7.62 mm
Base Number Matches	1

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74LV573

Octal D-type transparent latch; 3-state

Rev. 03 — 15 April 2009

Product data sheet

1. General description

The 74LV573 is a low-voltage Si-gate CMOS device that is pin and function compatible

with 74HC573 and 74HCT573.

The 74LV573 consists of eight D-type transparent latches, featuring separate D-type

inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable

(LE) input and an output enable (OE) input are common to all internal latches.

When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches

are transparent, that is, a latch output will change each time its corresponding D-input

changes. When LE is LOW, the latches store the information that was present at the

D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.

When OE is LOW, the contents of the eight latches are available at the outputs. When OE

is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does

not affect the state of the latches.

The 74LV573 is functionally identical to the 74LV373, but has a different pin arrangement.

2. Features

Wide operating voltage: 1.0 V to 5.5 V

Optimized for low voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V

= 2.7 V and V

= 3.6 V

Typical output ground bounce < 0.8 V at V

= 3.3 V and T

amb

= 25

°C

Typical HIGH-level output voltage (V

) undershoot: > 2 V at V

= 3.3 V and

amb

= 25

°C

Inputs and outputs on opposite sides of package allowing easy interface with

microprocessors

Useful as input or output port for microprocessors

Common 3-state output enable input

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

74LV573N,112相似产品对比

	74LV573N,112	74LV573PW,118	74LV573D,112	74LV573DB,112	74LV573DB,118	74LV573D,118
描述	IC OCTAL D TRANSP LATCH 20-DIP	IC OCTAL D TRANSP LATCH 20TSSOP	IC OCTAL D TRANSP LATCH 20SOIC	IC OCTAL D TRANSP LATCH 20SSOP	IC OCTAL D TRANSP LATCH 20SSOP	IC OCTAL D TRANSP LATCH 20SOIC
Brand Name	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor
是否Rohs认证	符合	符合	符合	符合	符合	符合
厂商名称	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)
零件包装代码	DIP	TSSOP2	SOP	SSOP2	SSOP2	SOP
包装说明	DIP, DIP20,.3	TSSOP, TSSOP20,.25	SOP, SOP20,.4	SSOP, SSOP20,.3	SSOP, SSOP20,.3	SOP, SOP20,.4
针数	20	20	20	20	20	20
制造商包装代码	SOT146-1	SOT360-1	SOT163-1	SOT339-1	SOT339-1	SOT163-1
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
其他特性	BROADSIDE VERSION OF 373	BROADSIDE VERSION OF 373	BROADSIDE VERSION OF 373	BROADSIDE VERSION OF 373	BROADSIDE VERSION OF 373	BROADSIDE VERSION OF 373
系列	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H	LV/LV-A/LVX/H
JESD-30 代码	R-PDIP-T20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20
JESD-609代码	e4	e4	e4	e4	e4	e4
长度	26.73 mm	6.5 mm	12.8 mm	7.2 mm	7.2 mm	12.8 mm
负载电容（CL）	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
逻辑集成电路类型	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
最大I（ol）	0.008 A	0.008 A	0.008 A	0.008 A	0.008 A	0.008 A
位数	8	8	8	8	8	8
功能数量	1	1	1	1	1	1
端口数量	2	2	2	2	2	2
端子数量	20	20	20	20	20	20
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
输出极性	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	DIP	TSSOP	SOP	SSOP	SSOP	SOP
封装等效代码	DIP20,.3	TSSOP20,.25	SOP20,.4	SSOP20,.3	SSOP20,.3	SOP20,.4
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	IN-LINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE
包装方法	TUBE	TAPE AND REEL	TUBE	TUBE	TAPE AND REEL	TAPE AND REEL
峰值回流温度（摄氏度）	260	260	260	260	260	260
电源	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	29 ns	29 ns	29 ns	29 ns	29 ns	29 ns
传播延迟（tpd）	53 ns	53 ns	53 ns	53 ns	53 ns	53 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	4.2 mm	1.1 mm	2.65 mm	2 mm	2 mm	2.65 mm
最大供电电压 (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压 (Vsup)	1 V	1 V	1 V	1 V	1 V	1 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	NO	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD
端子形式	THROUGH-HOLE	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	2.54 mm	0.65 mm	1.27 mm	0.65 mm	0.65 mm	1.27 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30	30	30	30	30
宽度	7.62 mm	4.4 mm	7.5 mm	5.3 mm	5.3 mm	7.5 mm
Base Number Matches	1	1	1	1	1	1
湿度敏感等级	-	1	1	1	1	1

74LV573N,112

74LV573N,112概述

74LV573N,112规格参数

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74LV573N,112相似产品对比

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