Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
salesaddresses@nexperia.com).
Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Rev. 13 — 7 February 2014
Product data sheet
1. General description
The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with
3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit
buffers or one 16-bit buffer. It features four output enable inputs, (1OE to 4OE) each
controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a
high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 V and 5 V applications.
The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground
bounce
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
All data inputs have bus hold. (74LVCH16244A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Temperature range
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Package
Name
74LVC16244ADL
74LVCH16244ADL
74LVC16244ADGG
74LVCH16244ADGG
74LVC16244AEV
74LVCH16244AEV
74LVC16244ABX
74LVCH16244ABX
HXQFN60
VFBGA56
TSSOP48
SSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT370-1
SOT362-1
Type number
plastic very thin fine-pitch ball grid array package; SOT702-1
56 balls; body 4.5
7
0.65 mm
plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4
6
0.5 mm
SOT1134-2
4. Functional diagram
1
1OE
48
2OE
25
3OE
24
4OE
1A0
1A1
17
1A2
1A3
1
1OE
25
2Y0
3OE
2A0
2A1
41
40
2A0
8
9
30
29
4A0
4Y0
19
20
2A2
2A3
2A1
2Y1
4A1
4Y1
3A0
3A1
38
2A2
2Y2
11
27
4A2
4Y2
22
3A2
3A3
4A0
23
4A1
4A2
4A3
001aae506
47
46
1A0
1Y0
2
3
36
35
3A0
3Y0
13
14
1A1
1Y1
3A1
3Y1
EN1
EN2
EN3
EN4
1
1
2
3
5
6
1
2
8
9
11
12
1
3
13
14
16
17
1
4
19
20
22
23
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
44
1A2
1Y2
5
33
3A2
3Y2
16
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
43
1A3
1Y3
6
32
3A3
3Y3
37
2A3
2OE
2Y3
12
26
4A3
4OE
4Y3
48
24
001aae231
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVC_LVCH16244A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 13 — 7 February 2014
2 of 19
NXP Semiconductors
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
V
CC
data input
to internal circuit
mna705
Fig 3.
Bus hold circuit
5. Pinning information
5.1 Pinning
1OE
1Y0
1Y1
GND
1Y2
1Y3
V
CC
2Y0
2Y1
1
2
3
4
5
6
7
8
9
48 2OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 V
CC
41 2A0
40 2A1
39 GND
38 2A2
37 2A3
36 3A0
35 3A1
34 GND
33 3A2
32 3A3
31 V
CC
30 4A0
29 4A1
28 GND
27 4A2
26 4A3
25 3OE
001aaj052
GND 10
2Y2 11
2Y3 12
3Y0 13
3Y1 14
GND 15
3Y2 16
3Y3 17
V
CC
18
4Y0 19
4Y1 20
GND 21
4Y2 22
4Y3 23
4OE 24
74LVC16244A
74LVCH16244A
ball A1
74LVCH16244A
index area
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
001aaj053
74LVC16244A
Transparent top view
Fig 4.
Pin configuration SOT370-1 (SSOP48) and
SOT362-1 (TSSOP48)
Fig 5.
Pin configuration SOT702-1 (VFBGA56)
74LVC_LVCH16244A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 13 — 7 February 2014
3 of 19
NXP Semiconductors
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
terminal 1
index area
D1
A32
A31
A30
A29
A28
A27
D4
A1
D5
B20
B19
B18
D8
A26
A2
B1
A3
B2
A4
B3
A5
B4
A6
B5
A7
B6
A8
B7
A9
GND
(1)
B11
B12
B15
B16
B17
A25
A24
A23
A22
74LVC16244A
74LVCH16244A
B14
A21
B13
A20
A19
A18
A10
D6
B8
B9
B10
D7
A17
D2
A11
A12
A13
A14
A15
A16
D3
001aaj054
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 6.
Pin configuration SOT1134-2 (HXQFN60)
74LVC_LVCH16244A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 13 — 7 February 2014
4 of 19
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
