74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
Rev. 10 — 19 July 2012
Product data sheet
1. General description
The 74HC4052; 74HCT4052 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4052B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4052; 74HCT4052 is a dual 4-channel analog multiplexer/demultiplexer with
common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to
nY3) and a common input/output (pin nZ). The common channel select logics include two
digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When
pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0
and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state,
independent of pins S0 and S1.
V
CC
and GND are the supply voltage pins for the digital control inputs (pins S0, S1 and E).
The V
CC
to GND ranges are 2.0 V to 10.0 V for the 74HC4052 and 4.5 V to 5.5 V for the
74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between V
CC
as a positive limit and V
EE
as a negative limit. V
CC
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically
ground).
2. Features and benefits
Wide analog input voltage range from
5
V to +5 V
Low ON resistance:
80
(typical) at V
CC
V
EE
= 4.5 V
70
(typical) at V
CC
V
EE
= 6.0 V
60
(typical) at V
CC
V
EE
= 9.0 V
Logic level translation: to enable 5 V logic to communicate with
5
V analog signals
Typical ‘break before make’ built-in
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4052
74HC4052N
74HC4052D
74HC4052DB
74HC4052PW
74HC4052BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
DIP16
SO16
SSOP16
TSSOP16
DHVQFN16
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body
width 3.9 mm
plastic shrink small outline package; 16 leads; body
width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic dual-in line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body
width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic dual-in line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
SOT38-4
SOT109-1
SOT338-1
SOT403-1
SOT763-1
Name
Description
Version
Type number
74HCT4052
74HCT4052N
74HCT4052D
74HCT4052DB
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
DIP16
SO16
SSOP16
TSSOP16
DHVQFN16
SOT38-4
SOT109-1
SOT338-1
SOT403-1
SOT763-1
74HCT4052PW
40 C
to +125
C
74HCT4052BQ
40 C
to +125
C
74HC_HCT4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 19 July 2012
2 of 29
NXP Semiconductors
74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
5. Functional diagram
10
13
1Z
1Y0
10
9
S0
S1
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
6
E
2Z
001aah824
0
1
G4
4
×
9
6
12
14
15
11
1
5
2
4
13
3
0
3
MDX
0
1
2
3
1
5
2
4
12
14
15
11
001aah825
2Y3
3
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
nYn
V
CC
V
EE
V
CC
V
CC
V
CC
from
logic
V
EE
nZ
V
EE
mnb043
Fig 3.
Schematic diagram (one switch)
74HC_HCT4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 19 July 2012
3 of 29
NXP Semiconductors
74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
V
DD
16
13
12
1Z
1Y0
14
1Y1
15
S0
10
1Y2
11
9
LOGIC
LEVEL
CONVERSION
1-OF-4
DECODER
1
1Y3
S1
2Y0
E
6
5
2Y1
2
2Y2
4
2Y3
3
8
V
SS
7
V
EE
2Z
001aah872
Fig 4.
Functional diagram
74HC_HCT4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 19 July 2012
4 of 29
NXP Semiconductors
74HC4052; 74HCT4052
Dual 4-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
74HC4052
74HCT4052
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
GND
1
2
3
4
5
6
7
8
001aah822
74HC4052
74HCT4052
16 V
CC
15 1Y2
2Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
V
EE
10 S0
9
S1
7
8
GND
S1
9
2Z
2Y3
2Y1
E
2
3
4
5
6
V
CC(1)
terminal 1
index area
16 V
CC
15 1Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
10 S0
2Y0
1
001aah823
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
supply pin or input.
Fig 5.
Pin configuration for DIP16, SO16 and
(T)SSOP16
Fig 6.
Pin configuration for DHVQFN16
6.2 Pin description
Table 2.
Symbol
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
GND
S1
S0
1Y3
1Y0
1Z
1Y1
1Y2
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
independent input or output 2Y0
independent input or output 2Y2
common input or output 2
independent input or output 2Y3
independent input or output 2Y1
enable input (active LOW)
negative supply voltage
ground (0 V)
select logic input 1
select logic input 0
independent input or output 1Y3
independent input or output 1Y0
common input or output 1
independent input or output 1Y1
independent input or output 1Y2
positive supply voltage
74HC_HCT4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 19 July 2012
5 of 29
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