74HC4538; 74HCT4538
Dual retriggerable precision monostable multivibrator
Rev. 03 — 8 June 2009
Product data sheet
1. General description
The 74HC4538; 74HCT4538 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC4538; 74HCT4538 are dual retriggerable-resettable monostable multivibrators.
Each multivibrator has an active LOW trigger/retrigger input (nA), an active HIGH
trigger/retrigger input (nB), an overriding active LOW direct reset input (nCD), an output
(nQ) and its complement (nQ), and two pins (nREXT/CEXT and nCEXT) for connecting
the external timing components C
EXT
and R
EXT
. Typical pulse width variation over the
specified temperature range is
±0.2
%.
The multivibrator may be triggered by either the positive or the negative edges of the input
pulse. The duration and accuracy of the output pulse are determined by the external
timing components C
EXT
and R
EXT
. The output pulse width (t
W
) is equal to
0.7
×
R
EXT
×
C
EXT
. The linear design techniques guarantee precise control of the output
pulse width. A LOW level at nCD terminates the output pulse immediately. Schmitt trigger
action on pins nA and nB makes the circuit highly tolerant of slower rise and fall times.
2. Features
I
I
I
I
I
Tolerant of slow trigger rise and fall times
Separate reset inputs
Triggering from falling or rising edge
Multiple package options
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
NXP Semiconductors
74HC4538; 74HCT4538
Dual retriggerable precision monostable multivibrator
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4538N
74HCT4538N
74HC4538D
74HCT4538D
74HC4538DB
74HCT4538DB
74HC4538PW
74HCT4538PW
−40 °C
to +125
°C
−40 °C
to +125
°C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
SOT403-1
−40 °C
to +125
°C
SO16
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
−40 °C
to +125
°C
Name
DIP16
Description
plastic dual in-line package; 16-leads (300 mil)
Version
SOT38-4
Type number
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
4. Functional diagram
2
1
1REXT/CEXT
1CEXT
1Q
5
4
1A
1B
1Q
6
7
3
1CD
2REXT/CEXT
2CEXT
14
15
2Q
11
12
2A
2B
2Q
10
9
13
2CD
001aae727
Fig 1.
Functional diagram
74HC_HCT4538_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 8 June 2009
2 of 24
NXP Semiconductors
74HC4538; 74HCT4538
Dual retriggerable precision monostable multivibrator
nB
nA
V
CC
nREXT/CEXT
V
ref1
nCEXT
GND
nCD
enable
power-on reset
V
CC
V
ref2
enable
nQ
nQ
mba338
GND
Fig 2.
Logic diagram (one multivibrator)
74HC_HCT4538_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 8 June 2009
3 of 24
NXP Semiconductors
74HC4538; 74HCT4538
Dual retriggerable precision monostable multivibrator
5. Pinning information
5.1 Pinning
74HC4538
74HCT4538
1CEXT
1REXT/CEXT
1CD
1B
1A
1Q
1Q
GND
1
2
3
4
5
6
7
8
001aak190
16 V
CC
15 2CEXT
14 2REXT/CEXT
13 2CD
12 2B
11 2A
10 2Q
9
2Q
1CEXT
1REXT/CEXT
1CD
1B
1A
1Q
1Q
GND
1
2
3
4
5
6
7
8
74HC4538
74HCT4538
16 V
CC
15 2CEXT
14 2REXT/CEXT
13 2CD
12 2B
11 2A
10 2Q
9
001aak191
2Q
Fig 3.
Pin configuration for DIP16 and SO16
Fig 4.
Pin configuration for SSOP16 and TSSOP16
5.2 Pin description
Table 2.
Symbol
1CEXT, 2CEXT
1REXT/CEXT, 2REXT/CEXT
1CD, 2CD
1B, 2B
1A, 2A
1Q, 2Q
1Q, 2Q
GND
V
CC
Pin description
Pin
1, 15
2, 14
3, 13
4, 12
5, 11
6, 10
7, 9
8
16
Description
external capacitor connection (always connected to ground)
external capacitor/resistor connection
direct reset input (active LOW)
input (LOW to HIGH triggered)
input (HIGH to LOW triggered)
output
complementary output (active LOW)
ground (0 V)
supply voltage
74HC_HCT4538_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 8 June 2009
4 of 24
NXP Semiconductors
74HC4538; 74HCT4538
Dual retriggerable precision monostable multivibrator
6. Functional description
Table 3.
Inputs
nA
↓
H
X
[1]
Function table
Outputs
nB
L
↑
X
nCD
H
H
L
L
H
nQ
nQ
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑
= positive-going transition;
↓
= negative-going transition;
= one HIGH level output pulse, with the pule width determined by C
EXT
and R
EXT
;
= one LOW level output pulse, with the pulse width determined by C
EXT
and R
EXT
.
(1)
(1)
(2)
(1)
nB input
(3)
nA input
(4)
nCD input
nREXT/CEXT input
V
ref1
V
ref2
V
ref1
V
ref2
nQ output
T
(5)
T
T
001aae737
(1) Positive edge triggering.
(2) Positive edge re-triggering (pulse lengthening).
(3) Negative edge triggering.
(4) Reset (pulse shortening).
(5) T = 0.7
×
R
EXT
×
C
EXT
(see also
Figure 6).
Fig 5.
Timing diagram
74HC_HCT4538_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 8 June 2009
5 of 24
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