74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
Rev. 7 — 19 July 2012
Product data sheet
1. General description
The 74HC4051; 74HCT4051 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). The device is specified in compliance with JEDEC
standard no. 7A.
The 74HC4051; 74HCT4051 is an 8-channel analog multiplexer/demultiplexer with three
digital select inputs (S0 to S2), an active-LOW enable input (E), eight independent
inputs/outputs (Y0 to Y7) and a common input/output (Z). With E LOW, one of the eight
switches is selected (low impedance ON-state) by S0 to S2. With E HIGH, all switches are
in the high-impedance OFF-state, independent of S0 to S2.
V
CC
and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
The V
CC
to GND ranges are 2.0 V to 10.0 V for 74HC4051 and 4.5 V to 5.5 V for
74HCT4051. The analog inputs/outputs (Y0 to Y7, and Z) can swing between V
CC
as a
positive limit and V
EE
as a negative limit. V
CC
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically
ground).
2. Features and benefits
Wide analog input voltage range from
5
V to +5 V
Low ON resistance:
80
(typical) at V
CC
V
EE
= 4.5 V
70
(typical) at V
CC
V
EE
= 6.0 V
60
(typical) at V
CC
V
EE
= 9.0 V
Logic level translation: to enable 5 V logic to communicate with
5
V analog signals
Typical ‘break before make’ built-in
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
NXP Semiconductors
74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4051N
74HCT4051N
74HC4051D
74HCT4051D
74HC4051DB
74HCT4051DB
74HC4051PW
74HCT4051PW
74HC4051BQ
74HCT4051BQ
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT109-1
SOT338-1
SOT403-1
SOT763-1
40 C
to +125
C
Name
DIP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
5. Functional diagram
V
CC
16
13 Y0
S0 11
14 Y1
15 Y2
S1 10
12 Y3
LOGIC
LEVEL
CONVERSION
S2 9
1-OF-8
DECODER
1 Y4
5 Y5
2 Y6
E 6
4 Y7
3 Z
8
GND
7
V
EE
001aad543
Fig 1.
74HC_HCT4051
Functional diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 19 July 2012
2 of 31
NXP Semiconductors
74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
11
10
9
6
0
8X
2
G8
0
7
13
S0
S1
S2
11
10
9
14
15
12
1
5
2
E
6
3
Z
4
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
3
MUX/DMUX
0
1
2
3
4
5
6
7
13
14
15
12
1
5
2
4
001aad541
001aad542
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
Y
V
CC
V
EE
V
CC
V
CC
V
CC
from
logic
V
EE
Z
V
EE
001aad544
Fig 4.
Schematic diagram (one switch)
74HC_HCT4051
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 19 July 2012
3 of 31
NXP Semiconductors
74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
74HC4051
74HCT4051
terminal 1
index area
Y6
16 V
CC
15 Y2
14 Y1
13 Y0
12 Y3
11 S0
10 S1
9
001aad539
74HC4051
74HCT4051
Y4
Y6
Z
Y7
Y5
E
V
EE
GND
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
GND
S2
9
V
CC(1)
16 V
CC
15 Y2
14 Y1
13 Y0
12 Y3
11 S0
10 S1
Z
Y7
Y5
E
V
EE
1
Y4
S2
001aad540
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 5.
Pin configuration DIP16, SO16, and (T)SSOP16
Fig 6.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
E
V
EE
GND
S0, S1, S2
Z
V
CC
Pin description
Pin
6
7
8
11, 10, 9
3
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
common output or input
supply voltage
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12, 1, 5, 2, 4 independent input or output
74HC_HCT4051
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 19 July 2012
4 of 31
NXP Semiconductors
74HC4051; 74HCT4051
8-channel analog multiplexer/demultiplexer
7. Functional description
7.1 Function table
Table 3.
Input
E
L
L
L
L
L
L
L
L
H
[1]
Function table
[1]
Channel ON
S2
L
L
L
L
H
H
H
H
X
S1
L
L
H
H
L
L
H
H
X
S0
L
H
L
H
L
H
L
H
X
Y0 to Z
Y1 to Z
Y2 to Z
Y3 to Z
Y4 to Z
Y5 to Z
Y6 to Z
Y7 to Z
switches off
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
CC
I
IK
I
SK
I
SW
I
EE
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
switch clamping current
switch current
supply current
supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16, (T)SSOP16, and
DHVQFN16 package
P
[1]
[2]
[3]
Conditions
[1]
Min
0.5
-
-
-
-
-
-
65
-
-
-
Max
+11.0
20
20
25
20
50
50
+150
750
500
100
Unit
V
mA
mA
mA
mA
mA
mA
C
mW
mW
mW
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
SW
<
0.5
V or V
SW
> V
CC
+ 0.5 V
0.5
V < V
SW
< V
CC
+ 0.5 V
power dissipation
per switch
To avoid drawing V
CC
current out of terminal Z, when switch current flows into terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no V
CC
current will flow out of terminals Yn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed V
CC
or V
EE
.
For DIP16 packages: above 70
C
the value of P
tot
derates linearly with 12 mW/K.
For SO16 packages: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60
C
the value of P
tot
derates linearly with 4.5 mW/K.
[2]
[3]
74HC_HCT4051
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 19 July 2012
5 of 31
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
