INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT377
Octal D-type flip-flop with data
enable; positive-edge trigger
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
FEATURES
•
Ideal for addressable register applications
•
Data enable for address and data synchronization
applications
•
Eight positive-edge triggered D-type flip-flops
•
See “273” for master reset version
•
See “373” for transparent latch version
•
See “374” for 3-state version
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
74HC/HCT377
The 74HC/HCT377 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT377 have eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. A common
clock (CP) input loads all flip-flops simultaneously when
the data enable (E) is LOW. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Q
n
) of the flip-flop.
The E input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay CP to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
13
77
3.5
20
HCT
14
53
3.5
20
ns
MHz
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
PIN DESCRIPTION
PIN NO.
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
SYMBOL
E
Q
0
to Q
7
D
0
to D
7
GND
CP
V
CC
NAME AND FUNCTION
data enable input (active LOW)
flip-flop outputs
data inputs
ground (0 V)
74HC/HCT377
clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
FUNCTION TABLE
OPERATING
MODES
load “1”
load “0”
hold (do nothing)
Notes
74HC/HCT377
INPUTS
CP
↑
↑
↑
X
E
l
l
h
H
D
n
h
l
X
X
OUTPUTS
Q
n
H
L
no change
no change
1. H = HIGH voltage level
h = HIGH voltage level one set-up time
prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time
prior to the LOW-to-HIGH CP transition
↑
= LOW-to-HIGH CP transition
X = don’t care
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
−40
to
+85
−40
to
+125
max.
240
48
41
110
22
19
120
24
20
90
18
15
90
18
15
3
3
3
4
4
4
4
20
24
ns
74HC/HCT377
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
min. typ. max. min. max. min.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
output transition time
44
16
13
19
7
6
80
16
14
60
12
10
60
12
10
3
3
3
4
4
4
6
30
35
14
5
4
14
5
4
6
2
2
−8
−3
−2
−3
−1
−1
23
70
83
160
32
27
75
15
13
100
20
17
75
15
13
75
15
13
3
3
3
4
4
4
5
24
28
200
40
34
95
19
16
t
THL
/ t
TLH
ns
Fig.6
t
W
clock pulse width
HIGH or LOW
set-up time
D
n
to CP
set-up time
E to CP
hold time
D
n
to CP
hold time
E to CP
maximum clock pulse
frequency
ns
Fig.6
t
su
ns
Fig.7
t
su
ns
Fig.7
t
h
ns
Fig.7
t
h
ns
Fig.7
f
max
MHz
Fig.6
December 1990
5
FPGA/CPLD
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