Important notice
Dear Customer,
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Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
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INTEGRATED CIRCUITS
DATA SHEET
User Guide
Product specification
Supersedes data of January 1993
File under Integrated Circuits, IC06
1997 Nov 25
Philips Semiconductors
Product specification
User Guide
CONTENTS
1
2
3
3.1
3.2
3.3
3.3.1
3.3.2
3.4
3.5
3.6
3.7
3.8
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5
5.1
5.2
5.3
6
INTRODUCTION
CONSTRUCTION
AC CHARACTERISTICS
Test conditions
Comparing the speed of HCMOS and LSTTL
Propagation delays and transition times
Supply voltage dependence of propagation
delay
Temperature dependence of propagation delay
Derating system for AC characteristics
Clock pulse requirements
System (parallel) clocking
Clock pulse considerations as functions of
maximum frequency
Minimum AC characteristics
POWER DISSIPATION
Static
Dynamic
Power dissipation capacitance
Input pulses
Conditions for C
PD
tests
Additional power dissipation in 74HCT devices
Power dissipation due to slow input rise/fall
times
Comparison with LSTTL power dissipation
SUPPLY VOLTAGE
Range
Battery back-up
Power supply regulation and decoupling
INPUT/OUTPUT PROTECTION
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
8.1
8.2
8.3
8.4
8.5
8.6
9
10
11
11.1
11.2
11.3
12
13
14
15
16
17
INPUT CIRCUITS
74HC inputs
74HCT inputs
Maximum input rise/fall times
Termination of unused inputs
Input current
Input capacitance
Coupling of adjacent inputs
Input voltage and forward diode input current
OUTPUT CIRCUITS
Output drive
Push-pull outputs
Three-state outputs
Open-drain outputs
Increased drive capability of gates
Output capacitance
STATIC NOISE IMMUNITY
DYNAMIC NOISE IMMUNITY
BUFFERED DEVICES
Definition
Output buffering
Input buffering
PERFORMANCE OF OSCILLATORS
LATCH-UP FREE
DROP-IN REPLACEMENTS FOR LSTTL
BUS SYSTEMS
PACKAGE PIN CAPACITANCE
POWER-ON RESET
NOTE:
THE INFORMATION IN THIS USER
GUIDE IS INTENDED AS A DESIGN-AID AND
DOES NOT CONSTITUTE A GUARANTEE.
1997 Nov 25
2
Philips Semiconductors
Product specification
User Guide
1
INTRODUCTION
The 74HC/HCT/HCU family is a comprehensive range of
high-speed CMOS (HCMOS) integrated circuits. Whilst
retaining all the advantages of CMOS technology - wide
operating voltage range, very low power consumption,
high input noise immunity and wide operating temperature
range - these circuits have the high-speed and drive
capabilities of low-power Schottky TTL (LSTTL). An
extensive product range (most TTL functions and some
devices from the successful HE4000B series: analog
multiplexers, long time-constant multivibrators,
phase-locked loops) and the aforementioned performance
open new avenues in system design.
For comparison, the key performance parameters of
HCMOS are shown with those of other technologies in
Table 1. The propagation delay of metal-gate CMOS ruled
out CMOS for many applications until the arrival of our
HE4000B series. Now, our 3
µm
gate HCMOS technology
has a speed comparable to LSTTL while retaining the
important CMOS qualities, see Fig.1.
Table 2 compares the operating characteristics of the
74HC and 74HCT IC types with those of LSTTL in more
detail. 74HC and 74HCT devices are ideal for use in new
equipment designs and, as alternatives to TTL devices, in
existing designs. The 74HCT circuits which are direct
replacements for LSTTL circuits also enhance
performance in many respects.
Fig.1
Propagation delay as a function of load
capacitance; V
CC
= 5 V, T
amb
= 25
°C.
1997 Nov 25
3
Table 1
Comparison of CMOS and TTL technologies; supply voltage V
CC
= 5 V; ambient temperature T
amb
= 25
°C;
load capacitance C
L
= 15 pF
1997 Nov 25
4
Philips Semiconductors
User Guide
HCMOS
technology
parameters
family
74HC
metal gate
CMOS
standard
TTL
low-power
Schottky
TTL
74LS
Schottky
TTL
advanced
low-power
Schottky
TTL
74ALS
advanced
Schottky
TTL
74AS
Fairchild
advanced
Schottky
TTL
74F
4000
CD
HE
74
74S
Power dissipation, typ. (mW)
Gate
Counter
static
dynamic @100 kHz
static
dynamic @100 kHz
0.0000025
0.075
0.000005
0.001
0.1
0.001
0.120
10
10
300
300
2
2
100
100
19
19
500
500
1.2
1.2
60
60
8.5
8.5
−
−
5.5
5.5
190
190
0.125
Propagation delay
(ns)
Gate
typical
maximum
8
14
94
190
40
80
10
20
9.5
15
3
5
4
7
1.5
2.5
3
4
Delay/power product
(pJ)
Gate
at 100 kHz
0.52
9
4
100
19
57
4.8
13
16.5
Maximum clock frequency
(MHz)
typical
D-type flip-flop
minimum
Counter
55
30
45
25
4
2
2
1
12
6
6
3
25
15
32
25
33
25
32
25
100
75
70
40
60
40
45
−
160
−
−
−
125
100
125
100
typical
minimum
Output drive
(mA)
standard outputs
bus outputs
Fan-out
(LS-loads)
standard outputs
bus outputs
10
15
1
4
2
40
120
20
60
50
160
20
60
50
120
50
160
4
6
0.51
0.8
1.6
16
48
8
24
20
64
8
24
20
48
20
64
Product specification
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