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INTEGRATED CIRCUITS
74AVC16834A
18-bit registered driver
with inverted register enable and
Dynamic Controlled Outputs™ (3-State)
Product data
Supersedes data of 2000 Jul 25
2002 Sep 11
Philips
Semiconductors
Philips Semiconductors
Product data
18-bit registered driver with inverted register enable
and Dynamic Controlled Outputs™ (3-State)
74AVC16834A
FEATURES
•
Wide supply voltage range of 1.2 V to 3.6 V
•
Complies with JEDEC standard no. 8-1A/5/7
•
CMOS low power consumption
•
Input/output tolerant up to 3.6 V
•
DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed
degradation
PIN CONFIGURATION
NC
NC
Y
0
GND
Y
1
Y
2
V
CC
Y
3
Y
4
Y
5
GND
Y
6
Y
7
Y
8
Y
9
Y
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
NC
A
0
GND
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
A
12
A
13
A
14
V
CC
A
15
A
16
GND
A
17
CP
GND
•
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
•
Power off disables 74AVC16834A outputs, permitting Live
•
Integrated input diodes to minimize input overshoot and
•
Full PC133 solution provided when used with PCK2509S or
PCK2510S and CBT16292
undershoot
Insertion
DESCRIPTION
The 74AVC16834A is a 18-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor (Live
Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to
support termination line drive during transient. See the graphs on
page 9 for typical curves.
Y
11
GND
Y
12
Y
13
Y
14
V
CC
Y
15
Y
16
GND
Y
17
OE
LE
SH00156
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.0 ns; C
L
= 30 pF.
SYMBOL
t
PHL
/t
PLH
PARAMETER
Propagation delay
An to Yn
Propagation delay
LE to Yn;
CP to Yn
Input capacitance
Power dissipation capacitance per buffer
V
I
= GND to V
CC1
Outputs enabled
Output disabled
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
CONDITIONS
TYPICAL
2.6
2.0
1.7
2.9
2.3
1.9
5.0
25
6
UNIT
ns
t
PHL
/t
PLH
C
I
C
PD
ns
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic 0.5 mm pitch TSSOP
56-Pin Plastic 0.4 pitch TSSOP (TVSOP)
TEMPERATURE
RANGE
–40°C to +85°C
–40°C to +85°C
ORDER CODE
74AVC16834ADGG
74AVC16834ADGV
DRAWING
NUMBER
SOT364-1
SOT481-2
2002 Sep 11
2
Philips Semiconductors
Product data
18-bit registered driver with inverted register enable
and Dynamic Controlled Outputs™ (3-State)
74AVC16834A
PIN DESCRIPTION
PIN NUMBER
1, 2, 55
3, 5, 6, 8, 9, 10, 12, 13,
14, 15, 16, 17, 19, 20,
21, 23, 24, 26
4, 11, 18, 25, 32, 39, 46,
53, 56
7, 22, 35, 50
27
28
30
54, 52, 51, 49, 48, 47,
45, 44, 43, 42, 41, 40,
38, 37, 36, 34, 33, 31
SYMBOL
NC
Y
0
to Y
17
NAME AND FUNCTION
No connection
Data outputs
LOGIC SYMBOL
OE
GND
V
CC
OE
LE
CP
A
0
to A
17
Ground (0 V)
CP
Positive supply voltage
Output enable input
(active LOW)
Latch enable input
(active LOW)
Clock input
Data inputs
A
1
D
LE
CP
Y
1
LE
TO THE 17 OTHER CHANNELS
SH00202
TYPICAL INPUT (DATA OR CONTROL)
V
CC
A1
SH00200
2002 Sep 11
3
Philips Semiconductors
Product data
18-bit registered driver with inverted register enable
and Dynamic Controlled Outputs™ (3-State)
74AVC16834A
LOGIC SYMBOL (IEEE/IEC)
OE
CP
LE
27
30
28
C3
G2
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
Y
13
Y
14
Y
15
Y
16
Y
17
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
1
∇
1
3D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
EN1
2C3
FUNCTION TABLE
INPUTS
OE
H
L
L
L
L
L
L
H
L
X
Z
↑
=
=
=
=
=
LE
X
L
L
H
H
H
H
CP
X
X
X
↑
↑
H
L
A
X
L
H
L
H
X
X
OUTPUTS
Z
L
H
L
H
Y
01
Y
02
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
LOW-to-HIGH level transition
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
SH00158
168-pin SDR SDRAM DIMM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
BACK SIDE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE
74AVCM16834 74AVCM16834 74AVCM16834
PCK2509S or PCK2510S
The PLL clock distribution device and AVCM registered drivers reduce signal loads on the memory
controller and prevent timing delays and waveform distortions that would cause unreliable operation
SDRAM
SW00407
2002 Sep 11
4
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