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74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
Rev. 2 — 3 July 2012
Product data sheet
1. General description
The 74AUP2T1326 is a high-performance, dual supply, low-power, low-voltage, dual
buffer/line driver with output enable circuitry.
The 74AUP2T1326 is designed for logic-level translation and combines the functions of
the 74AUP1G32 and 74AUP2G126. The buffer/line driver is controlled by two output
enable inputs (1OE and 2OE). A logic LOW on input 1OE causes the output 2Y to assume
a high-impedance OFF-state, a logic LOW on 2OE causes the output 3Y to assume a
high-impedance OFF-state. The output 1Y is the result of a logic OR of the two output
enable inputs.
The output enable inputs (1OE and 2OE) are Schmitt trigger inputs, they switch at
different voltages for positive and negative-going signals. The difference between the
positive voltage V
T+
and the negative voltage V
T
is defined as the input hysteresis
voltage V
H
. The output enable inputs accept standard input signals and are capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals
Both V
CC(A)
and V
CC(B)
can be supplied at any voltage between 1.1 V and 3.6 V making
the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V,
1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are
referenced to V
CC(A)
and pins A, 2Y and 3Y are referenced to V
CC(B)
.
The device ensures low static and dynamic power consumption and is fully specified for
partial power down applications using I
OFF
. The I
OFF
circuitry disables the outputs,
preventing any damaging backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range:
V
CC(A)
: 1.1 V to 3.6 V; V
CC(B)
: 1.1 V to 3.6 V.
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 2A exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
NXP Semiconductors
74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP2T1326GF
40 C
to +85
C
Name
XSON10
Description
Version
plastic extremely thin small outline package; no leads; SOT1081-2
10 terminals; body 1 x 1.7 x 0.5 mm
Type number
4. Marking
Table 2.
Marking
Marking code
[1]
pf
Type number
74AUP2T1326GF
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1OE
6
Rpd
8
1Y
2OE
7
Rpd
V
CC(A)
9
A
3
2
V
CC(B)
2Y
3Y
001aaj301
R
pd
= Internal pull-down resistor.
Fig 1.
Logic symbol
74AUP2T1326
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 July 2012
2 of 17
NXP Semiconductors
74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
74AUP2T1326
V
CC(B)
1
10
n.c.
3Y
2
9
2Y
A
3
8
1Y
V
CC(A)
4
7
2OE
GND
5
6
001aaj302
1OE
Transparent top view
Fig 2.
Pin configuration SOT1081-2 (XSON10)
6.2 Pin description
Table 3.
Symbol
V
CC(B)
3Y
A
V
CC(A)
GND
1OE
2OE
1Y
2Y
n.c.
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
Description
supply voltage B
data output
data input
supply voltage A
ground (0 V)
output enable input (Schmitt trigger input)
output enable input (Schmitt trigger input)
data output
data output
not connected
74AUP2T1326
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 July 2012
3 of 17
NXP Semiconductors
74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
7. Functional description
Table 4.
Input
1OE
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
2OE
L
H
H
L
L
H
H
A
X
L
H
L
H
L
H
1Y
L
H
H
H
H
H
H
2Y
Z
Z
Z
L
H
L
H
3Y
Z
L
H
Z
Z
L
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(A)
V
CC(B)
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+4.6
+4.6
-
+4.6
-
+4.6
20
50
-
+150
250
Unit
V
V
mA
V
mA
V
mA
mA
mA
C
mW
V
I
< 0 V
[1]
-50
0.5
50
0.5
-
-
-50
65
[2]
[1]
[2]
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CCO
T
amb
=
40 C
to +85
C
[3]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
V
CCO
is the supply voltage associated with an output pin.
For XSON10 package: above 45
C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC(A)
V
CC(B)
V
I
V
O
Recommended operating conditions
Parameter
supply voltage A
supply voltage B
input voltage
output voltage
[1]
Conditions
Min
1.1
1.1
0
0
Max
3.6
3.6
3.6
V
CCO
Unit
V
V
V
V
74AUP2T1326
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 July 2012
4 of 17
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