74VCX16240
Low−Voltage 1.8/2.5/3.3V
16−Bit Buffer
With 3.6 V−Tolerant Inputs and Outputs
(3−State, Inverting)
The 74VCX16240 is an advanced performance, inverting 16−bit
buffer. It is designed for very high−speed, very low−power operation
in 1.8 V, 2.5 V or 3.3 V systems.
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
to 3.3 V busses. It is guaranteed to be over−voltage tolerant to 3.6 V.
The 74VCX16240 is nibble controlled with each nibble functioning
identically, but independently. The control pins may be tied together to
obtain full 16−bit operation. The 3−state outputs are controlled by an
Output Enable (OEn) input for each nibble. When OEn is LOW, the
outputs are on. When OEn is HIGH, the outputs are in the high
impedance state.
Features
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MARKING DIAGRAM
48
48
1
VCX16240
AWLYYWW
TSSOP−48
DT SUFFIX
CASE 1201
A
WL
YY
WW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
•
Designed for Low Voltage Operation: V
CC
= 1.65 V
−
3.6 V
•
3.6V Tolerant Inputs and Outputs
•
High Speed Operation: 2.5 ns max for 3.0 V to 3.6 V
•
•
•
•
•
•
•
3.0 ns max for 2.3 V to 2.7 V
6.0 ns max for 1.65 V to 1.95 V
Static Drive:
±24
mA Drive at 3.0 V
±18
mA Drive at 2.3 V
±6
mA Drive at 1.65 V
Supports Live Insertion and Withdrawal
I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
Near Zero Static Supply Current in All Three Logic States (20
mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds
±250
mA @ 125°C
ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
All Devices in Package TSSOP are Inherently Pb−Free*
ORDERING INFORMATION
Device
74VCX16240DT
74VCX16240DTR
Package
TSSOP
(Pb−Free)
TSSOP
(Pb−Free)
Shipping
†
39 / Rail
2500 / Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
−
Rev. 5
1
Publication Order Number:
74VCX16240/D
74VCX16240
OE1 1
O0 2
O1 3
GND 4
O2 5
O3 6
V
CC
7
O4 8
O5 9
GND 10
O6 11
O7 12
O8 13
O9 14
GND 15
O10 16
O11 17
V
CC
18
O12 19
O13 20
GND 21
O14 22
O15 23
OE4 24
48 OE2
47 D0
46 D1
45 GND
44 D2
43 D3
42 V
CC
41 D4
40 D5
39 GND
38 D6
37 D7
36 D8
35 D9
34 GND
33 D10
32 D11
31 V
CC
30 D12
29 D13
28 GND
27 D14
26 D15
25 OE3
D0:3
O0:3
D8:11
O8:11
OE1
OE2
1
48
OE3
OE4
25
24
D4:7
O4:7
D12:15
O12:15
One of Four
Figure 2. Logic Diagram
OE1
48
OE2
25
OE3
24
OE4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
1
1
1
EN1
EN2
EN3
EN4
1
1
∇
2
3
5
6
8
9
11
2
∇
3
∇
12
13
14
16
4
∇
17
19
20
22
23
Figure 1. 48−Lead Pinout
(Top View)
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
Figure 3. IEC Logic Diagram
Table 1. PIN NAMES
Pins
OEn
D0−D15
O0−O15
Function
Output Enable Inputs
Inputs
Outputs
TRUTH TABLE
OE1
L
L
H
D0:3
L
H
X
O0:3
H
L
Z
OE2
L
L
H
D4:7
L
H
X
O4:7
H
L
Z
OE3
L
L
H
D8:11
L
H
X
O8:11
H
L
Z
OE4
L
L
H
D12:15
L
H
X
O12:15
H
L
Z
H = High Voltage Level;
L = Low Voltage Level;
Z = High Impedance State;
X = High or Low Voltage Level and Transitions Are Acceptable, for I
CC
reasons, DO NOT FLOAT Inputs
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2
74VCX16240
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Value
−0.5
to +4.6
−0.5
≤
V
I
≤
+4.6
−0.5
≤
V
O
≤
+4.6
−0.5
≤
V
O
≤
V
CC
+ 0.5
DC Input Diode Current
DC Output Diode Current
−50
−50
+50
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
±50
±100
±100
−65
to +150
Output in 3−State
Note 1; Outputs Active
V
I
< GND
V
O
< GND
V
O
> V
CC
Condition
Unit
V
V
V
V
mA
mA
mA
mA
mA
mA
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. I
O
absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
I
OH
I
OL
I
OH
I
OL
I
OH
I
OL
T
A
Dt/DV
Supply Voltage
Input Voltage
Output Voltage
HIGH Level Output Current, V
CC
= 3.0 V
−
3.6 V
LOW Level Output Current, V
CC
= 3.0 V
−
3.6 V
HIGH Level Output Current, V
CC
= 2.3 V
−
2.7 V
LOW Level Output Current, V
CC
= 2.3 V
−
2.7 V
HIGH Level Output Current, V
CC
= 1.65 V
−
1.95 V
LOW Level Output Current, V
CC
= 1.65 V
−
1.95 V
Operating Free−Air Temperature
Input Transition Rise or Fall Rate, V
IN
from 0.8 V to 2.0 V, V
CC
= 3.0 V
−40
0
(Active State)
(3−State)
Parameter
Operating
Data Retention Only
Min
1.65
1.2
−0.3
0
0
Typ
3.3
3.3
Max
3.6
3.6
3.6
V
CC
3.6
−24
24
−18
18
−6
6
+85
10
Unit
V
V
V
mA
mA
mA
mA
mA
mA
°C
ns/V
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3
74VCX16240
DC ELECTRICAL CHARACTERISTICS
T
A
=
−40°C
to +85°C
Symbol
V
IH
Characteristic
HIGH Level Input Voltage (Note 2)
Condition
1.65 V
≤
V
CC
< 2.3 V
2.3 V
≤
V
CC
≤
2.7 V
2.7 V < V
CC
≤
3.6 V
V
IL
LOW Level Input Voltage (Note 2)
1.65 V
≤
V
CC
< 2.3 V
2.3 V
≤
V
CC
≤
2.7V
2.7 V < V
CC
≤
3.6 V
V
OH
HIGH Level Output Voltage
1.65 V
≤
V
CC
≤
3.6 V; I
OH
=
−100
mA
V
CC
= 1.65 V; I
OH
=
−6
mA
V
CC
= 2.3 V; I
OH
=
−6
mA
V
CC
= 2.3 V; I
OH
=
−12
mA
V
CC
= 2.3 V; I
OH
=
−18
mA
V
CC
= 2.7 V; I
OH
=
−12
mA
V
CC
= 3.0 V; I
OH
=
−18
mA
V
CC
= 3.0 V; I
OH
=
−24
mA
V
OL
LOW Level Output Voltage
1.65 V
≤
V
CC
≤
3.6 V; I
OL
= 100
mA
V
CC
= 1.65 V; I
OL
= 6 mA
V
CC
= 2.3 V; I
OL
= 12 mA
V
CC
= 2.3 V; I
OL
= 18 mA
V
CC
= 2.7 V; I
OL
= 12 mA
V
CC
= 3.0 V; I
OL
= 18 mA
V
CC
= 3.0 V; I
OL
= 24 mA
I
I
I
OZ
I
OFF
I
CC
Input Leakage Current
3−State Output Current
Power−Off Leakage Current
Quiescent Supply Current (Note 3)
1.65 V
≤
V
CC
≤
3.6 V; 0 V
≤
V
I
≤
3.6 V
1.65 V
≤
V
CC
≤
3.6 V; 0 V
≤
V
O
≤
3.6 V;
V
I
= V
IH
or V
IL
V
CC
= 0 V; V
I
or V
O
= 3.6 V
1.65 V
≤
V
CC
≤
3.6 V; V
I
= GND or V
CC
1.65 V
≤
V
CC
≤
3.6 V; 3.6 V
≤
V
I
, V
O
≤
3.6 V
DI
CC
Increase in I
CC
per Input
2.7 V < V
CC
≤
3.6 V; V
IH
= V
CC
−
0.6 V
2. These values of V
I
are used to test DC electrical characteristics only.
3. Outputs disabled or 3−state only.
V
CC
−
0.2
1.25
2.0
1.8
1.7
2.2
2.4
2.2
0.2
0.3
0.4
0.6
0.4
0.4
0.55
±5.0
±10
10
20
±20
750
mA
mA
mA
mA
mA
mA
V
Min
0.65 x V
CC
1.6
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Unit
V
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4
74VCX16240
AC CHARACTERISTICS
(Note 4; t
R
= t
F
= 2.0 ns; C
L
= 30 pF; R
L
= 500
W)
T
A
=
−40°C
to +85°C
V
CC
= 3.0 V to 3.6 V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Parameter
Propagation Delay
Input to Output
Output Enable Time to
High and Low Level
Output Disable Time From
High and Low Level
Output−to−Output Skew
(Note 5)
Waveform
1
2
2
Min
0.8
0.8
0.8
0.8
0.8
0.8
Max
2.5
2.5
3.5
3.5
3.5
3.5
0.5
0.5
V
CC
= 2.3 V to 2.7 V
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
3.0
3.0
4.1
4.1
3.8
3.8
0.5
0.5
V
CC
= 1.65 to 1.95V
Min
1.5
1.5
1.5
1.5
1.5
1.5
Max
6.0
6.0
8.2
8.2
7.8
7.8
0.75
0.75
Unit
ns
ns
ns
ns
4. For C
L
= 50 pF, add approximately 300 ps to the AC maximum specification.
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
OSHL
) or LOW−to−HIGH (t
OSLH
); parameter
guaranteed by design.
AC CHARACTERISTICS
(t
R
= t
F
= 2.0 ns; C
L
= 50 pF; R
L
= 500
W)
T
A
=
−40°C
to +85°C
V
CC
= 3.0V to 3.6V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Parameter
Propagation Delay
Input to Output
Output Enable Time to
High and Low Level
Output Disable Time From
High and Low Level
Output−to−Output Skew
(Note 6)
Waveform
3
4
4
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
3.9
3.9
5.0
5.0
4.4
4.4
0.5
0.5
Min
V
CC
= 2.7V
Max
5.3
5.3
6.1
6.1
4.8
4.8
0.5
0.5
Unit
ns
ns
ns
ns
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
OSHL
) or LOW−to−HIGH (t
OSLH
); parameter
guaranteed by design.
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