74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs
July 1997
Revised April 2005
74VHCT374A
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The VHCT374A is an advanced high speed CMOS octal
flip-flop with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type flip-
flop is controlled by a clock input (CP) and an output
enable input (OE). When the OE input is HIGH, the eight
outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1:
Outputs in OFF-State.
Features
s
High speed: f
MAX
140 MHz (typ) at T
A
2.0V, V
IL
25
q
C
s
High noise immunity: V
IH
0.8V
s
Power down protection is provided on all inputs and out-
puts
s
Low power dissipation:
I
CC
4
P
A (max) @ T
A
25
q
C
s
Pin and function compatible with 74HCT374
Ordering Code:
Order Number
74VHCT374AM
74VHCT374ASJ
74VHCT374AMTC
74VHCT374AN
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
© 2005 Fairchild Semiconductor Corporation
DS500030
www.fairchildsemi.com
74VHCT374A
Pin Descriptions
Pin Names
D
0
–D
7
CP
OE
O
0
–O
7
Description
Data Inputs
Clock Pulse Input 3-STATE
Output Enable Input 3-STATE
Outputs
Truth Table
Inputs
D
n
H
L
X
CP
Outputs
OE
L
L
H
O
n
H
L
Z
X
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
LOW-to-HIGH Transition
Functional Description
The VHCT374A consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74VHCT374A
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
(Note 3)
(Note 4)
Input Diode Current (I
IK
)
Output Diode Current (I
OK
)
(Note 5)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
q
C
0.5V to
7.0V
0.5V to
7.0V
0.5V to V
CC
0.5V
0.5V to
7.0V
20 mA
r
20 mA
r
25 mA
r
75 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 6)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
(Note 3)
(Note 4)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
5.0V
r
0.5V
0 ns/V
a
20 ns/V
Note 2:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 3:
HIGH or LOW state. I
OUT
absolute maximum rating must be
observed.
Note 4:
When outputs are in OFF-State or when V
CC
Note 5:
V
OUT
GND, V
OUT
!
V
CC
(Outputs Active).
Note 6:
Unused inputs must be held HIGH or LOW. They may not float.
OV.
4.5V to
5.5V
0V to
5.5V
0V to V
CC
0V to 5.5V
40
q
C to
85
q
C
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
V
OL
I
OZ
I
IN
I
CC
I
CCT
I
OFF
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
3-STATE Output
OFF-State Current
Input Leakage Current
Quiescent Supply Current
Maximum I
CC
/Input
Output Leakage Current
(Power Down State)
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
4.5
5.5
0–5.5
5.5
5.5
0.0
4.40
3.94
0.0
0.1
0.36
4.50
T
A
Min
2.0
2.0
0.8
0.8
4.40
3.80
0.1
0.44
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
2.0
2.0
0.8
0.8
Min
Units
V
V
V
V
V
V
V
IN
Conditions
V
IH
I
OH
50
P
A
or V
IL
I
OH
8 mA
V
IN
V
IH
I
OL
50 uA
or V
IL
I
OL
8 mA
V
IN
V
OUT
V
IN
V
IN
V
IN
V
OUT
V
IH
or V
IL
V
CC
or GND
5.5V or GND
V
CC
or GND
3.4V
V
CC
or GND
5.5V
r
0.25
r
0.1
4.0
1.35
0.5
r
2.5
r
1.0
40.0
1.50
5.0
P
A
P
A
P
A
mA
Other Inputs
P
A
Noise Characteristics
Symbol
V
OLP
(Note 7)
V
OLV
(Note 7)
V
IHD
(Note 7)
V
ILD
(Note 7)
Note 7:
Parameter guaranteed by design.
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
T
A
Typ
1.2
25
q
C
Limits
1.6
Units
V
V
V
V
C
L
C
L
C
L
C
L
Conditions
50 pF
50 pF
50 pF
50 pF
1.2
1.6
2.0
0.8
3
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74VHCT374A
AC Electrical Characteristics
Symbol
t
PLH
t
PHL
t
PZL
t
PZH
t
PLZ
t
PHZ
t
OSLH
t
OSHL
f
MAX
C
IN
C
OUT
C
PD
Maximum Clock Frequency
Input
Capacitance
Output Capacitance
Power Dissipation Capacitance
|t
PLH max
t
PLH min
|; t
OSHL
Parameter
Propagation Delay Time
3-STATE Output Enable Time
3-STATE Output Disable Time
Output to Output Skew
V
CC
(V)
5.0
r
0.5
5.0
r
0.5
5.0
r
0.5
5.0
r
0.5
T
A
Min
25
q
C
Typ
4.1
5.6
6.5
7.3
7.0
Max
9.4
10.4
10.2
11.2
11.2
1.0
T
A
40
q
C to
85
q
C
Max
10.5
11.5
11.5
12.5
12.0
1.0
80
75
1.0
1.0
1.0
1.0
1.0
Min
Units
ns
ns
ns
R
L
R
L
Conditions
C
L
C
L
1 k
:
C
L
C
L
1 k
:
C
L
15 pF
50 pF
15 pF
50 pF
50 pF
(Note 8)
C
L
C
L
V
CC
V
CC
Open
5.0V
15 pF
50 pF
5.0
r
0.5
90
85
140
130
4
9
25
|t
PHL max
t
PHL min
|
MHz
10
pF
pF
pF
10
(Note 9)
Note 8:
Parameter guaranteed by design. t
OSLH
Note 9:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.) C
PD
* V
CC
* f
IN
I
CC
/8 (per F/F). The total C
PD
when n pcs. of the octal D Flip-Flop operates
can be calculated by the equation: C
PD
(total) 20
12m.
AC Operating Requirements
Symbol
t
W
(H)
t
W
(L)
t
S
t
H
Parameter
Minimum Pulse
Width (CP)
Minimum Set-up Time
Minimum Hold Time
V
CC
(V)
5.0
r
0.5
5.0
r
0.5
5.0
r
0.5
T
A
Min
6.5
2.5
2.5
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Min
8.5
2.5
2.5
Units
ns
ns
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4
74VHCT374A
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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