Ordering number : ENA0782A
LC87F2416A
CMOS LSI
8-bit Microcontroller
16K-byte Flash ROM / 512-byte RAM / 36-pin
http://onsemi.com
Overview
The LC87F2416A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 16K-byte Flash ROM
(On-board-programmable), 512-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be
divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two
8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous
SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO
interface, a UART interface (full duplex), two 12-bit PWM channels, a 12-bit/8-bit 10-channel AD converter, a
system clock frequency divider, an internal reset and a 20-source 10-vector interrupt feature.
Features
Flash ROM
•
Capable of On-board-programming with wide range (2.2 to 5.5V) of voltage source.
•
Block-erasable in 128 byte units
•
16384 × 8 bits (LC87F2416A)
RAM
•
512 × 9 bits (LC87F2416A)
Minimum bus cycle time
•
83.3ns (12MHz at VDD = 2.7V to 5.5V)
•
100ns (10MHz at VDD = 2.2V to 5.5V)
•
250ns (4MHz at VDD = 1.8V to 5.5V)
Note: The bus cycle time here refers to the ROM read speed.
Minimum instruction cycle time
•
250ns (12MHz at VDD = 2.7V to 5.5V)
•
300ns (10MHz at VDD = 2.2V to 5.5V)
•
750ns (4MHz at VDD = 1.8V to 5.5V)
QFP36
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 28 of this data sheet.
Semiconductor Components Industries, LLC, 2014
August, 2014
82114HKPC 20070319-S00003 No.A0782-1/28
LC87F2416A
Ports
•
Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1 bit units
Ports I/O direction can be designated in 4 bit units
•
Dedicated oscillator ports/input ports
•
Reset pin
•
Power pins
16 (P1n, P20, P21, P30, P31, P70 to P73)
8 (P0n)
2 (CF1/XT1, CF2/XT2)
____
1 ( RES)
3 (VSS1, VSS2, VDD1)
Timers
•
Timer 0: 16-bit timer/counter with a capture register.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an
8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + with an 8-bit prescaler 8-bit timer/counter (with
toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the
lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
•
Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts are programmable in 5 different time schemes
3) Base timer does not operate when selecting CF Oscillation circuit.
High-speed clock counter
1) Capable of counting clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Capable of generating real-time output.
SIO
•
SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
•
SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
No.A0782-2/28
LC87F2416A
UART
•
Full duplex
•
7/8/9 bit data bits selectable
•
1 stop bit (2-bit in continuous data transmission)
•
Built-in baudrate generator
AD converter: 12 bits/8 bits
×
10 channels
•
12 bits/8 bits AD converter resolution selectable
PWM: Multifrequency 12-bit PWM
×
2 channels
Remote control receiver circuit (sharing pins with P73, INT3, and T0IN)
•
Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
Clock output function
•
Capable of outputting selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 as system clock.
•
Capable of outputting oscillation clock of sub clock.
Watchdog timer
•
External RC watchdog timer
•
Interrupt and reset signals selectable
Interrupts
•
20 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4
INT3/INT5/base timer
T0H
T1L/T1H
SIO0/UART1 receive
SIO1/UART1 transmit
ADC/T6/T7/PWM4, PWM5
Port 0
Interrupt Source
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine stack levels: 256levels (the stack is allocated in RAM.)
No.A0782-3/28
LC87F2416A
High-speed multiplication/division instructions
•
16 bits
×
8 bits
(5 tCYC execution time)
•
24 bits
×
16 bits
(12 tCYC execution time)
•
16 bits
÷
8 bits
(8 tCYC execution time)
•
24 bits
÷
16 bits
(12 tCYC execution time)
Oscillation circuits
•
RC oscillation circuit (internal)
: For system clock
•
Frequency variable RC oscillation circuit (internal) : For system clock
•
CF oscillation circuit
: For system clock, with internal Rf
•
Crystal oscillation circuit
: For low-speed system clock, with internal Rf
1) CF and crystal oscillation circuit have a shared terminal, and it is software selectable.
2) When reset, CF and Crystal oscillators stop operation. After reset is released, CF oscillator starts operation.
System clock divider function
•
Capable of running with low current consumption.
•
The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs
(at a main clock rate of 10MHz).
Internal reset function
•
Power-On-Reset (POR) function
1) POR resets the system when the power supply voltage is applied.
2) POR release level is selectable from 5 levels (1.55V, 1.72V, 2.00V, 2.37V, 2.65V) by option.
•
Low Voltage Detection reset (LVD) function
1) LVD used with POR resets the system when the supply voltage is applied and when it is lowered.
2) LVD function is selectable from enable/disable and the reset level is selectable from 3 levels (1.90V, 2.25V,
2.50V) by option.
Standby function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, INT2, and INT4 pins to the specified level
(3) Having an interrupt source established at port 0
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, and INT4 pins to the specified level
(3) Having an interrupt source established at port
(4) Having an interrupt source established in the base timer circuit
Note: X'tal HOLD mode can be used only when crystal oscillation is selected.
No.A0782-4/28
LC87F2416A
Onchip-Debugger
•
Supports software debugging with the IC mounted on the target board.
•
For a small pin package, two-channel Onchip-Debugger port ((DBGP0(P0), DBGP1(P1)) are equipped.
Flash data security
•
Protects from illegal access to data in flash memory.
Note: Flash data security cannot guarantee perfect security.
Package form
•
QFP36 (7
×
7): Lead-free type
Development tools
•
Onchip Debugger : TCB87 TypeB + LC87F2416A
Flash ROM programming boards
Package
QFP36 (7×7)
Programming boards
W87F24Q
■
Flash ROM programmer
Maker
Single
Flash Support
Group, Inc.
Gang
Model
AF9708/AF9709/AF9709B
(including product of Ando Electric Co.,Ltd)
AF9723 (Main body)
(including product of Ando Electric Co.,Ltd)
AF9833 (Unit)
(including product of Ando Electric Co.,Ltd)
Our Company
SKK Type-B( SANYOFWS)
Application Version : 1.03 or later
Chip Data Version : 2.03 or later
LC87F2416A
Supported version (Note)
Revision : After 02.60
Device
LC87F2416A
For information about AF series, please contact the following:
Flash Support Group, Inc.
TEL: 053-459-1030
E-mail: sales@j-fsg.co.jp
Same package and pin assignment as mask ROM version.
1) LC872400 series options can be set by using flash ROM data. Thus the board used for mass production can be used
for debugging and evaluation without modifications.
2) If the program for the mask ROM version is used, the usable ROM/RAM capacity is the same as the mask ROM
version.
No.A0782-5/28
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