DATASHEET
ISL6141, ISL6151
Negative Voltage Hot Plug Controller
The ISL6141 is an 8-pin, negative voltage hot plug controller
that allows a board to be safely inserted and removed from a
live backplane. Inrush current is limited to a programmable
value by controlling the gate voltage of an external N-
channel pass transistor. The pass transistor is turned off if
the input voltage is less than the Under-Voltage threshold, or
greater than the Over-Voltage threshold. The IntelliTrip
TM
electronic circuit breaker and programmable current limit
features protect the system against short circuits. When the
Over-Current threshold is exceeded, the output current is
limited for 600s before the circuit breaker shuts down the
FET. If the fault disappears before the 600s time-out,
normal operation resumes. In addition, the IntelliTrip
TM
electronic circuit breaker has a fast Hard Fault shutdown
with a threshold set at 4 times the current limit value. When
activated, the GATE is immediately turned off and then
slowly turned back on for a single retry (soft-start). The
active low PWRGD signal can be used to directly enable a
power module (with a low enable input). The ISL6151 is the
same device but has an active high PWRGD output.
FN9079
Rev 2.00
November 9, 2015
Features
• Operates from -20V to -80V (-100V Absolute Max Rating)
• Programmable Inrush Current
• Programmable Over-Voltage Protection
• Programmable Under-Voltage Protection
- 135mV of hysteresis
- Equals ~4.6V of hysteresis at the power supply
• UVLO (Under-Voltage Lock-Out) ~ 16.5V
• Programmable Current Limit with 600s time-out
• IntelliTrip
TM
electronic circuit breaker distinguishes
between Over-Current and Hard Fault conditions
- Fast shutdown for Hard Faults with a single retry (fault
current > 4X current limit value).
• Pin Compatible with ISL6140/50.
• Power Good Control Output
- Monitors both the DRAIN (voltage drop across the FET)
and the GATE voltage; once both are OK, the Power
Good output is latched in the active state.
- PWRGD active high: ISL6151 (H version)
- PWRGD active low: ISL6141 (L version)
• Pb-free available
Typical Application (RL, CL are the Load)
GND
R4
UV
R5
OV
R6
V
EE
SENSE
GATE
C1
R3
DRAIN
C2
RL
-48V IN
R1
Q1
-48V OUT
(LOAD)
CL
V
DD
PWRGD
GND
ISL6141
Applications
• VoIP (Voice over Internet Protocol) Servers
• Telecom systems at -48V
• Negative Power Supply Control
• +24V Wireless Base Station Power
R2
Related Literature
• ISL6140/41 EVAL1 Board Set, Document # AN9967
• ISL6142/52 EVAL1 Board Set, Document # AN1000
• ISL6140/50 Hot Plug Controller, Document # FN9039
• ISL6116 Hot Plug Controller, Document # FN4778
NOTE: See www.intersil.com/hotplug for more information.
R1 = 0.02 (1%)
R2 = 10 (5%)
R3 = 18k (5%)
R4 = 549k (1%)
R5 = 6.49k (1%)
R6 = 10k (1%)
C1 = 150nF (25V)
C2 = 3.3nF (100V)
Q1 = IRF530 (100V, 17A, 0.11)
CL = 100F (100V)
RL = equivalent load
Pinout
ISL6141 OR ISL6151 (8 LEAD SOIC)
PWRGD/PWRGD
OV
UV
V
EE
1
2
3
4
8 V
DD
TOP VIEW
7 DRAIN
6 GATE
5 SENSE
ISL6141 has active low (L version) PWRGD output pin
ISL6151 has active high (H version) PWRGD output pin
FN9079 Rev 2.00
November 9, 2015
Page 1 of 20
ISL6141, ISL6151
Ordering Information
PART NO.
ISL6141CBZA (See Note)
ISL6151CBZA (See Note)
(No longer available or supported)
ISL6141IBZA (See Note)
ISL6151IBZA (See Note)
(No longer available or supported)
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
GND
V
DD
GND
TEMP. RANGE (
o
C)
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
(RoHS Compliant)
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead SOIC
PKG. DWG. #
M8.15
M8.15
M8.15
M8.15
-
R4
1.265V +
+
-
V
EE
V
EE
-
1.255V +
+
-
V
EE
+
1.255V -
+
-
V
EE
-
210mV +
+
-
V
EE
GATE
-
50mV +
+
-
V
EE
CURRENT
LIMIT
REGULATOR
-
11.1V +
+
-
V
EE
1.3V
+
-
V
EE
-
+
UVLO
REGULATOR,
REFERENCES
UV
13V
UV
R5
OV
OV
LOGIC
TIMING
GATE DRIVE
R6
HARD
FAULT
OUTPUT
DRIVE
LATCH
LOGIC
PWRGD
(ISL6141)
PWRGD
(ISL6151)
600s
TIMER
GATE
PWRGD
PWRGD
V
EE
SENSE
GATE
R3
R2
C1
C2
DRAIN
LOAD
CL
RL
-48V IN
R1
Q1
-48V OUT
FIGURE 1. BLOCK DIAGRAM
FN9079 Rev 2.00
November 9, 2015
Page 2 of 20
ISL6141, ISL6151
Pin Descriptions
PWRGD (ISL6141; L Version) Pin 1
This digital output is an open-drain pull-down device. During
start-up the DRAIN and GATE voltages are monitored with
two separate comparators. The first comparator looks at the
DRAIN pin voltage compared to the internal V
PG
reference
(V
PG
is nominal 1.3V); this measures the voltage drop across
the external FET and sense resistor. When the DRAIN to V
EE
voltage drop is less than 1.3V, the first of two conditions
required for the power to be considered good are met. In
addition, the GATE voltage monitored by the second
comparator must be within approximately 2.5V of its normal
operating voltage (13.6V). When both criteria are met the
PWRGD output will transition from high to low, enabling a
power module in some applications. The output is latched in
the low state until any of the signals that shut off the GATE
occur (Over-Voltage, Under-Voltage, Under-Voltage Lock-Out,
Over-Current Time-Out, or powering down). Any of these
conditions will re-set the latch and the PWRGD output will
transition from low to high indicating power is no longer good.
In this case the output pull-down device shuts off, and the pin
becomes high impedance. Typically an external pull-up of
some kind is used to pull the pin high (many brick regulators
have a pull-up function built in).
external FET. The built in 25mV hysteresis will keep the
GATE off until the OV pin drops below 1.230V, which is the
nominal high to low threshold. A typical application will use
an external resistor divider from V
DD
to V
EE
to set the OV
level as desired. A three-resistor divider can be used to set
both OV and UV trip points.
UV (Under-Voltage) Pin 3 -
This analog input compares the
voltage on the pin to an internal comparator with a built in
hysteresis of 135mV. When the UV input goes below the
nominal reference (high to low transition) voltage of 1.120V,
the GATE pin is immediately pulled low to shut off the
external FET. Since the comparator has a built in 135mV
hysteresis the GATE will remain off until the UV pin rises
above a 1.255V low to high threshold. A typical application
will use an external resistor divider from V
DD
to V
EE
to set
the UV level as desired. A three-resistor divider can be used
to set both OV and UV trip points.
The UV pin is also used to reset the Over-Current latch. The
pin must be cycled below 1.120V (nominal) and then above
1.255V (nominal) to clear the latch and initiate a normal
power-up sequence.
V
EE
Pin 4 -
This is the most negative supply voltage, such
as in a -48V system. Most of the other signals are
referenced relative to this pin, even though it may be far
away from what is considered a GND reference.
SENSE Pin 5 -
This analog input monitors the voltage drop
across the external sense resistor (between SENSE and
V
EE
) to determine if the current exceeds the programmed
Over-Current trip point, equal to 50mV / Rsense. If the load
current exceeds the Over-Current threshold, the circuit will
regulate the current to maintain the nominal voltage drop
(50mV) across the sensing resistor R1 (Rsense). If current is
limited for more than 600s, the Over-Current shutdown
(also called electronic circuit breaker) will quickly turn off the
FET and latch the GATE pin off.
A Hard Fault comparator is employed to detect and respond
quickly to severe short circuits. The threshold of this
comparator is set approximately four times higher (210mV)
than the Over-Current trip point. When its threshold is
exceeded the GATE is immediately (10s typical) shut off,
the timer is reset, and a single retry (soft start) is attempted
before latching the GATE off (assuming the fault remains).
During the retry, if the fault disappears prior to the Over-
Current Time-Out period (600s) the FET will remain on as
normal. If the GATE is latched off, the user must either
toggle the UV pin below then above its threshold, or reduce
the supply voltage below the V
DD
UVLO trip point and then
above it. This will clear the latch and initiate a normal power-
up sequence.
PWRGD (ISL6151; H Version) Pin 1 -
This digital
output is used to provide an active high signal to enable an
external module. The Power Good comparators are the
same as described above, but the active state of the output
is reversed (reference Figure 33).
If the latch is reset (GATE turns off), the internal DMOS
device (Q3) is turned off, and Q2 (NPN) turns on to clamp
the output one diode drop above the DRAIN voltage to
produce a logic low.
Once the latch is set (both DRAIN and GATE are normal), the
DMOS device (Q3) turns on and sinks current to V
EE
through
a 6.2K resistor. The base of Q2 is clamped to V
EE
to turn it
off. If the external pull-up current is high enough (>1mA, for
example), the voltage drop across the resistor will be large
enough to produce a logic high output (in this example, 1mA *
6.2k = 6.2V) and enable the external module.
Note that for all H versions, although this is a digital pin
functionally, the logic high level is determined by the external
pull-up device, and the power supply to which it is
connected; the IC will not clamp it below the V
DD
voltage.
Therefore, if the external device does not have its own
clamp, or if it would be damaged by a high voltage, an
external clamp might be necessary.
OV (Over-Voltage) Pin 2 -
This analog input compares the
voltage on the pin to an internal voltage reference of 1.255V
(nominal). When the input goes above the reference (low to
high transition) an Over-Voltage condition is detected and
the GATE pin is immediately pulled low to shut off the
FN9079 Rev 2.00
November 9, 2015
Page 3 of 20
ISL6141, ISL6151
GATE Pin 6
- This analog output drives the gate of the
external FET used as a pass transistor. The GATE pin is
high (FET is on) when the following conditions are met:
•
•
•
•
UVLO is above its trip point (~16.5V)
Voltage on the UV pin is above its trip point (1.255V)
Voltage on the OV pin is below its trip point (1.255V)
No Over-Current conditions are present.
If any of the 4 conditions are violated, the GATE pin will be
pulled low to shut off or regulate current through the FET.
The GATE is latched off only when the 600s Over-Current
Time-Out period is exceeded.
The GATE is driven high by a weak (-50A nominal) pull-up
current source, in order to slowly turn on the FET. It is driven
low by a 70mA nominal pull-down device for three of the
above shut-off conditions. A larger (350mA nominal) pull-
down current shuts off the FET very quickly in the event of a
hard fault where the sense pin voltage exceeds
approximately 210mV.
DRAIN Pin 7 -
This is the analog input to one of two
comparators that control the PWRGD (ISL6141) or PWRGD
(ISL6151) outputs. It compares the voltage of the external
FET DRAIN to a 1.3V internal reference (V
PG
). The DRAIN
voltage is criticized only until the PWRGD or PWRGD
outputs are latched into their active low or high states. The
latch is reset when any of the conditions that turn off the
GATE occur (UVLO, OV, UV, OC Time-Out). Note that the
comparator does NOT itself turn off the GATE.
V
DD
Pin 8 -
This is the most positive power supply pin. It
can range from the Under-Voltage Lock-Out threshold
(16.5V) to +80V (Relative to V
EE
).
FN9079 Rev 2.00
November 9, 2015
Page 4 of 20
ISL6141, ISL6151
.
Absolute Maximum Ratings
Supply Voltage (V
DD
to V
EE
). . . . . . . . . . . . . . . . . . . . -0.3V to 100V
DRAIN, PWRGD, PWRGD Voltage . . . . . . . . . . . . . . . -0.3V to 100V
UV, OV Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V
SENSE, GATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 20V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V
Thermal Information
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Temperature Range (Commercial). . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . 36V to 72V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. PWRGD is referenced to DRAIN; V
PWRGD
-V
DRAIN
= 0V.
Electrical Specifications
V
DD
= +48V, V
EE
= +0V Unless Otherwise Specified. All tests are over the full temperature range; either
Commercial (0
o
C to 70
o
C) or Industrial (-40
o
C to 85
o
C). Typical specs are at 25
o
C.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
Units
PARAMETER
DC PARAMETERS
V
DD
PIN
Supply Operating Range
Supply Current
UVLO High
UVLO Low
UVLO hysteresis
GATE PIN
GATE Pin Pull-Up Current
GATE Pin Pull-Down Current
GATE Pin Pull-Down Current
GATE Pin Pull-Down Current
External GATE Drive (V
DD
= 20V, 80V)
GATE High Threshold (PWRGD/PWRGD
active)
SENSE PIN
Current Limit Trip Voltage
Hard Fault Trip Voltage
SENSE Pin Current
UV PIN
UV Pin High Threshold Voltage
UV Pin Low Threshold Voltage
UV Pin Hysteresis
V
DD
I
DD
V
UVLOH
V
UVLOL
UV = 3V; OV = V
EE
; SENSE = V
EE
; V
DD
=
80V
V
DD
Low to High transition
V
DD
High to Low transition
20
-
2.4
80
4.5
19
17
V
mA
V
V
V
15
13
16.7
14.8
1.9
I
PU
I
PD1
I
PD2
I
PD3
V
GATE
V
GH
GATE Drive on, V
GATE =
V
EE
GATE Drive off, UV or OV false
GATE Drive off, Over-Current Time-Out
GATE Drive off; Hard Fault (Vsense > 210mV)
(V
GATE -
V
EE)
, 20V <=V
DD
<=80V
V
GATE
- V
GATE
-30
-50
70
70
350
-60
A
mA
mA
mA
12
13.6
2.5
15
V
V
V
CL
V
HFT
I
SENSE
V
CL
= (V
SENSE
- V
EE
)
V
HFTV
= (V
SENSE
- V
EE
)
V
SENSE
= 50mV
40
50
210
-1.3
60
mV
mV
-4.0
A
V
UVH
V
UVL
V
UVHY
UV Low to High Transition
UV High to Low Transition
1.240
1.105
1.255
1.120
135
1.270
1.145
V
V
mV
FN9079 Rev 2.00
November 9, 2015
Page 5 of 20
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
