Data Sheet
FEATURES
Ultralow noise floor: −165.9 dBc/Hz or −165.2 dBc/Hz
(LVPECL or LVDS) at 2000 MHz
Configurable to LVPECL or pseudo LVDS outputs
2.5 V or 3.3 V LVPECL operation (LVDS 2.5 V only)
Wideband: 10 MHz to 3500 MHz operating frequency range
Flexible input interface
LVPECL, LVDS, CML, and CMOS compatible
AC or dc coupling
On-chip 50 kΩ pull-up/pull-down resistors to VDD and
GND
Multiple output drivers
Up to 8 differential or 16 single-ended LVPECL or LVDS
outputs
Low speed digital control via the IN_SEL and CONFIG pins
28-lead, 5 mm × 5 mm, LFCSP package, 25 mm
2
Low Noise, 2:8 Differential
Fanout Buffer
HMC6832
GENERAL DESCRIPTION
The
HMC6832
is an input selectable, 2:8 differential fanout
buffer designed for low noise clock distribution. The IN_SEL
control pin selects one of the two differential inputs. This input
is then buffered to all eight differential outputs. The low jitter
outputs of the
HMC6832
lead to synchronized low noise
switching of downstream circuits, such as mixers, analog-to-
digital converters (ADCs)/digital-to-analog converters (DACs),
or serializer/deserializer (SERDES) devices. The device is capable
of low voltage, positive emitter-coupled logic (LVPECL) or low
voltage differential signaling (LVDS) configurations by pulling
the CONFIG pin low for LVPECL or high or open (internally
pulled high) for pseudo LVDS.
PRODUCT HIGHLIGHTS
1.
Multiple Output Configurations.
The CONFIG pin allows the user to select LVPECL or
LVDS output termination.
Multiple Supply Voltage Operation.
The
HMC6832
operates at 2.5 V or 3.3 V for LVPECL
terminations (2.5 V only for LVDS).
Low Noise.
The
HMC6832
noise is low, typically from −168 dBc/Hz to
−162 dBc/Hz up to 3000 MHz.
Low Propagation Delay.
The
HMC6832
displays a low delay, less than 207 ps,
typical. Channel skew is also low, ±5 ps, typical.
Low Core Current.
The
HMC6832
has a low core current of 56 mA, typical.
APPLICATIONS
SONET, Fibre Channel, GigE clock distribution
ADC/DAC clock distribution
Low skew and jitter clocks
Wireless/wired communications
Level translation
High performance instrumentation
Medical imaging
Single-ended to differential conversions
2.
3.
4.
5.
Rev. C
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Trademarks and registered trademarks are the property of their respective owners.
HMC6832
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
AC Output Characteristics .......................................................... 4
Output Gain and Power Characteristics ................................... 5
Timing Characteristics ................................................................ 8
Timing Specifications .................................................................. 8
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
Data Sheet
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 12
Test Circuits ..................................................................................... 18
Theory of Operation ...................................................................... 19
Input Stage ................................................................................... 19
LVPECL Output Stage ............................................................... 19
Applications Information .............................................................. 21
Recommended Solder Reflow Profile...................................... 21
Evaluation Printed Circuit Board (PCB) ................................ 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
1/2018—Rev. B to Rev. C
Added Figure 24; Renumbered Sequentially .............................. 15
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
9/2016—Rev. A to Rev. B
Changes to Features Section and General Description Section . 1
Changes to Figure 1 .......................................................................... 3
Changes to Table 1 and Table 2 ....................................................... 4
Changes Table 3 ................................................................................ 5
Changes to Floor Density Jitter Parameter, Test Conditions/
Comments Column Only, Table 4 and Integrated RMS Jitter,
Test Conditions/Comments Column Only, Table 4..................... 6
Changes to Single-Sideband (SSB Phase Noise Floor) Parameter,
Test Conditions/Comments Column Only, Table 5..................... 8
Changes to Figure 11 Caption and Figure 15 Caption .............. 13
Changes to Figure 16 Caption to Figure 18 Caption and
Figure 20 Caption ........................................................................... 14
Changes to Figure 19 and Figure 21............................................. 14
Added Figure 23; Renumbered Sequentially ......................................15
Changes to Figure 22 Caption and Figure 24 Caption to
Figure 27 Caption ........................................................................... 15
Changes to Figure 28 Caption ...................................................... 16
Changes to Figure 38 Caption, Figure 40 Caption, and Figure 42 . 18
Changes to Input Stage Section and Figure 44 ........................... 19
Changes to Figure 45...................................................................... 20
Changes to Figure 50 Caption and Figure 51 Caption .............. 21
3/2016—Revision A: Initial Version
Rev. C | Page 2 of 23
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
VDD
50kΩ
INP1
50kΩ
100pF
OUTP6
VDD
50kΩ
INN1
50kΩ
OUTP4
OUTN4
LVDS
4mA
4mA
4mA
OUTN6
100pF
OUTP5
OUTN5
LVDS
4mA
4mA
LVDS
4mA
4mA
IN_SEL
HIGH: IN1
LOW: IN0
HMC6832
OUTP7
OUTN7
LVDS
4mA
VDD
50kΩ
INP0
50kΩ
100pF
OUTP1
VDD
50kΩ
INN0
50kΩ
4mA
VDD
100kΩ
CONFIG
HIGH: LVDS
LOW: LVPECL
OUTN1
100pF
OUTP0
OUTN0
LVDS
4mA
VAC_REF
4mA
LVDS
4mA
4mA
OUTP2
OUTN2
LVDS
4mA
4mA
OUTP3
OUTN3
LVDS
4mA
LVPECL
Figure 1.
Rev. C | Page 3 of 23
13201-001
CONFIGURATION
CONTROL
LVDS
2mA
HMC6832
SPECIFICATIONS
Data Sheet
Typical is given as f
INPUT
= 1.25 GHz (ac-coupled), differential input power = 7.5 dBm, T
NOMINAL
= 25°C, unless otherwise noted. All outputs
captured using 50 Ω scope termination. 50 Ω board termination on inputs used to minimize reflections.
Table 1.
Parameter
DC INPUT CHARACTERISTICS
VDD
LVPECL
LVDS
Input Common-Mode Voltage
SELECTION PINS
IN_SEL Pin
Input Voltage Low (V
IL
)
Input Voltage High (V
IH
)
CONFIG Pin
Input Voltage Low (V
IL
)
Input Voltage High (V
IH
)
TEMPERATURE RANGE, T
A
SUPPLY CURRENT
Core Current
Full Load Current
LVPECL Termination
LVDS Termination
RF INPUT CHARACTERISTICS
Operating Frequency Range
Input Swing (Single-Ended)
Input Capacitance
Pull-Up/Pull-Down Resistance
1
Min
Typ
Max
Unit
Test Conditions/Comments
2.375
3.0
2.375
GND + 0.2
2.5
3.3
2.5
VDD/2
2.625
3.6
2.625
VDD − 0.2
V
V
V
V
2.5 V operation
3.3 V operation
Guaranteed by design
GND = IN0, VDD = IN1
VDD/2 − 0.4
VDD/2 + 0.4
2VDD/3 − 0.3
2VDD/3 + 0.3
−40
+25
56
56
301
283
125
10
0.1
3.6
50
3500
2
+85
V
V
GND = LVPECL, VDD = LVDS
V
V
°C
mA
mA
mA
mA
mA
MHz
V
pF
kΩ
Outputs unterminated
VDD = 2.5 V
VDD = 3.3 V
R
TERM1
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω
See Figure 1
For LVPECL termination, R
TERM
is the single-ended termination resistance to GND. For LVDS termination, R
TERM
is the differential termination resistance.
AC OUTPUT CHARACTERISTICS
Table 2.
Parameter
DIFFERENTIAL OUTPUT VOLTAGE SWING
LVPECL Termination
LVDS Termination
OUTPUT VOLTAGE, HIGH LEVEL
LVPECL Termination
LVDS Termination
OUTPUT VOLTAGE, COMMON LEVEL
LVPECL Termination
LVDS Termination
Min
Typ
Max
Unit
Test Conditions/Comments
Differential inputs and outputs; adjusted for impedance
mismatch and printed circuit board (PCB) losses; see Figure 41
and Figure 42 for ac measurement test circuits
R
TERM
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω, VDD = 2.5 V
Differential inputs and outputs
R
TERM
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω, VDD = 2.5 V
Differential inputs and outputs; see Figure 39 and Figure 40
for dc measurement test circuits
R
TERM
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω, VDD = 2.5 V
652
721
462
1.63
2.51
1.65
mV p-p
mV p-p
mV p-p
V
V
V
1.30
2.15
1.42
V
V
V
Rev. C | Page 4 of 23
Data Sheet
Parameter
OUTPUT VOLTAGE, LOW LEVEL
LVPECL Termination
LVDS Termination
AC PERFORMANCE
3 dB Bandwidth
LVPECL Differential Input
1600
2500
3200
1750
2550
4100
56
57
45
59
59
46
50
50
50
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
%
%
%
Min
Typ
0.97
1.79
1.19
Max
Unit
V
V
V
HMC6832
Test Conditions/Comments
Differential inputs and outputs
R
TERM
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω, VDD = 2.5 V
See Figure 41 and Figure 42 for ac measurement test
circuits
Adjusted for impedance mismatch and PCB losses; refer to
Figure 19 and Figure 21
Differential input = 100 mV p-p; VDD = 2.5 V
Differential input = 200 mV p-p; VDD = 2.5 V
Differential input = 400 mV p-p; VDD = 2.5 V
Differential input = 100 mV p-p; VDD = 2.5 V
Differential input = 200 mV p-p; VDD = 2.5 V
Differential input = 400 mV p-p; VDD = 2.5 V
Differential inputs and outputs
R
TERM
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω, VDD = 2.5 V
Differential inputs and outputs
R
TERM
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω, VDD = 2.5 V
Differential inputs and outputs
R
TERM
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω, VDD = 2.5 V
50 kHz, 100 mV p-p sinusoidal signal modulated onto VDD;
single-ended 1 GHz, 0 dBm input; outputs measured
differentially
R
TERM
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω, VDD = 2.5 V
LVDS Differential Input
Output Rise Time (20% to 80%)
LVPECL Termination
LVDS Termination
Output Fall Time (20% to 80%)
LVPECL Termination
LVDS Termination
Duty Cycle Variation
LVPECL Termination
LVDS Termination
Power Supply Rejection Ratio
LVPECL Termination
LVDS Termination
−55
−59
−52
dBc
dBc
dBc
OUTPUT GAIN AND POWER CHARACTERISTICS
Table 3.
Parameter
DIFFERENTIAL SMALL SIGNAL GAIN (S21)
LVPECL Termination
25
26
22
dB
dB
dB
R
TERM
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω, VDD = 2.5 V
1250 MHz, adjusted for impedance
mismatch and PCB losses
R
TERM
= 86 Ω, VDD = 2.5 V
R
TERM
= 150 Ω, VDD = 3.3 V
R
TERM
= 100 Ω, VDD = 2.5 V
VDD = 2.5 V, adjusted for impedance
mismatch and PCB losses
−4 dBm = 399 mV p-p
−2 dBm = 502 mV p-p
−5 dBm = 356 mV p-p
Min
Typ
Max
Unit
Test Conditions/Comments
Adjusted for impedance mismatch and
printed circuit board (PCB) losses
LVDS Termination
INPUT 1 dB COMPRESSION POINT (P1dB)
LVPECL Termination
LVDS Termination
SATURATED POWER IN FUNDAMENTAL
TONE (SINGLE-ENDED)
LVPECL Termination
1000 MHz
2000 MHz
3000 MHz
−25
−25
−26
dBm
dBm
dBm
−4
−2
−5
Rev. C | Page 5 of 23
dBm
dBm
dBm
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