Si 5 9 8 / S i 5 9 9
10–810 M H
Z
I
2
C P
ROGRAMMABLE
XO/VCXO
Features
I
2
C programmable output
frequencies from 10 to 810 MHz
0.5 ps RMS phase jitter
Superior power supply rejection:
0.3–0.4 ps additive jitter
Available LVPECL, CMOS, LVDS,
and CML outputs
1.8, 2.5, or 3.3 V supply
Pin- and register-compatible with
Si570/571
Programmable with 28 parts per
trillion frequency resolution
Integrated crystal provides stability
and low phase noise
Frequency changes up to
±3500 ppm are glitchless
–40 to 85 °C operation
Industry-standard 5x7 mm package
Si5602
Applications
Ordering Information:
SONET / SDH / xDSL
Ethernet / Fibre Channel
3G SDI / HD SDI
Multi-rate PLLs
Multi-rate reference clocks
Frequency margining
Digital PLLs
CPU / FPGA FIFO control
Adaptive synchronization
Agile RF local oscillators
See page 21.
Pin Assignments:
See page 20.
(Top View)
SDA
7
NC
1
2
3
8
SCL
6
5
4
V
DD
Description
The Si598 XO/Si599 VCXO utilizes Silicon Laboratories' advanced DSPLL®
circuitry to provide a low-jitter clock at any frequency. They are user-
programmable to any output frequency from 10 to 810 MHz with 28 parts per
trillion (PPT) resolution. The device is programmed via a 2-pin I
2
C compatible
serial interface. The wide frequency range and ultra-fine programming resolution
make these devices ideal for applications that require in-circuit dynamic frequency
adjustments or multi-rate operation with non-integer related rates. Using an
integrated crystal, these devices provide stable low jitter frequency synthesis and
replace multiple XOs, clock generators, and DAC controlled VCXOs.
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
OE
Power Supply Filtering
Si598
SDA
Fixed
Frequency
Oscillator
Any Frequency
DSPLL®
10 to 810 MHz
Clock Synthesis
CLK+
CLK–
7
V
C
1
2
3
8
SCL
6
5
4
V
DD
Vc
(Si599)
OE
CLK–
CLK+
ADC
I2C Interface
GND
SDA
SCL
GND
Si599
Rev. 1.1 6/18
Copyright © 2018 by Silicon Laboratories
Si598/Si599
Si598/Si599
T
ABLE
Section
OF
C
ONTENTS
Page
1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2. I
2
C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Si598 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Si599 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8. Si59x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Rev. 1.1
2
Si598/Si599
1. Detailed Block Diagrams
V
DD
GND
f
XTAL
M
DCO
f
osc
÷HS_DIV
÷N1
CLKOUT+
CLKOUT–
RFREQ
OE
SDA
SCL
Control
Interface
NVM
RAM
Figure 1. Si598 Detailed Block Diagram
V
DD
GND
f
XTAL
V
C
ADC
VCADC
+
M
DCO
f
osc
÷HS_DIV
÷N1
CLKOUT+
CLKOUT–
RFREQ
OE
SDA
SCL
Control
Interface
NVM
RAM
Figure 2. Si599 Detailed Block Diagram
Rev. 1.1
3
Si598/Si599
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
3.3 V option
Supply Voltage
1
V
DD
2.5 V option
1.8 V option
Output enabled
LVPECL
CML
LVDS
CMOS
Tristate mode
Output Enable (OE)
2
,
Serial Data (SDA),
Serial Clock (SCL)
Operating Temperature Range
T
A
V
IH
V
IL
2.97
2.25
1.71
—
—
—
—
—
0.75 x V
DD
—
–40
3.3
2.5
1.8
120
108
99
90
60
—
—
—
3.63
2.75
1.89
130
120
110
100
75
—
0.5
85
V
V
V
mA
mA
mA
mA
mA
V
V
ºC
Supply Current
I
DD
Notes:
1.
Selectable parameter specified by part number. See Section 7. Ordering Information on page 21 for further details.
2.
OE pin includes a 17 k pullup resistor to V
DD
for OE Active High Option. OE pin includes 17 k
pull down for OE
Active Low. See Section “7.Ordering Information”.
Table 2. V
C
Control Voltage Input (Si599)
(Typical values TA = 25 ºC, V
DD
= 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Control Voltage Tuning Slope
1,2,3
K
V
10 to 90% of V
DD
—
—
—
—
—
–5
–10
9.3
500
—
45
95
125
185
380
±1
±5
10.0
—
50
V
DD
/2
—
—
—
—
—
—
+5
+10
10.7
—
—
—
V
DD
ppm/V
ppm/V
ppm/V
ppm/V
ppm/V
%
%
kHz
k
pF
V
V
Control Voltage Linearity
4
Modulation Bandwidth
V
C
Input Impedance
V
C
Input Capacitance
Nominal Control Voltage
Control Voltage Tuning Range
L
VC
BW
Z
VC
C
VC
V
CNOM
V
C
BSL
Incremental
@ f
O
—
0
Notes:
1.
Positive slope; selectable option by part number. See 7. Ordering Information on page 21.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
K
V
variation is ±10% of typical values.
4.
BSL determined from deviation from best straight line fit with V
C
ranging from 10 to 90% of V
DD
. Incremental slope
determined with V
C
ranging from 10 to 90% of V
DD
.
4
Rev. 1.1
Si598/Si599
Table 3. CLK± Output Frequency Characteristics
(Typical values TA = 25 ºC, V
DD
= 3.3 V, min/max limits VDD = 1.8 ±5%, 2.5 or 3.3 V ±10%, TA = –40 to 85 ºC unless otherwise
noted)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Programmable Frequency
Range
1,2,3
f
O
LVPECL/LVDS/CML
CMOS
Temp stability = ±20 ppm
10
10
—
—
—
—
—
—
—
—
810
160
±30
±50
±100
MHz
MHz
ppm
ppm
ppm
ppm
ppm
ms
Total Stability (Si598)
1,2,4,5
Temp stability = ±25 ppm
Temp stability = ±50 ppm
Temperature Stability (Si599)
1,5
Absolute Pull Range
1,5
(Si599)
Powerup Time
6
APR
t
OSC
T
A
= –40 to +85 ºC
–20
–50
±10
—
—
—
—
—
+20
+50
±370
10
Notes:
1.
See Section 7. Ordering Information on page 21 for further details.
2.
Specified at time of order by part number. Three frequency grades are available:
Grade A covers 10 to 810 MHz.
Grade B covers 10 to 280 MHz.
Grade C covers 10 to 160 MHz.
3.
Nominal output frequency set by V
CNOM
= 1/2 x V
DD
.
4.
Includes initial accuracy, temperature drift, shock, vibration, power supply and load drift. ±100 ppm and ±50 ppm
options include 15 years aging at 70 °C. ±30 ppm option includes 10 years aging at 40 °C.
5.
Selectable parameter specified by part number. See 7. Ordering Information on page 21.
6.
Time from power up or tristate mode to f
O
.
Rev. 1.1
5
FPGA/CPLD
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