MDT10P41A1
1. General Description
This EPROM-Based 8-bit Micro-controller uses a
fully static CMOS technology to achieve high
speed, small size, low power and high noise
immunity. Internal RC oscillator
On chip memory includes 1K words of EPROM,
and 31 bytes of static RAM.
transmitters/receivers,
pointing
devices,
and
telecommunications processors, such as Remote
controller,
small
instruments,
chargers,
toy,
automobile and PC peripheral … etc.
4. Pin Assignment
2. Features
u
u
u
u
Fully CMOS static design
8-bit data bus
On chip ROM size :1 K words
Internal RAM size : 31 bytes
(25 general purpose registers, 6 special
registers)
u
u
u
u
u
34 single word instructions
14-bit instructions
2-level stacks
Operating voltage : 2.3V ~ 5.5 V
Addressing modes include direct, indirect
and relative addressing modes
u
u
u
Power-on Reset
Internal RC oscillator : 6.5MHz ~ 7.5MHz
12 I/O pins with their own independent
direction control
MDT10P41A1P / MDT10P41A1S
PB4
PB5
PB6
PB7
Vdd
NC
NC
PA0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PB3
PB2
PB1
PB0
Vss
PA3
PA2
PA1
3. Applications
The application areas of this MDT10P41A1 range
from appliance motor control and high speed
automotive
to
low
power
remote
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
1 of 11
2005/6 Ver.1.6
MDT10P41A1
5. Block Diagram
Stack Two
Levels
10 bits
10 bits
EPROM
1024×14
14
bits
RAM
25×8
Port A
Port
PA0~PA3
4 bits
Program Counters
Instruction
Register
Special Register
Port PB0
D0~D7
Port PB1
Port B
Instruction
Decoder
Internal RC
Data
8bit
Port
PB2 ~PB3
Port
PB4 ~PB7
Control Circuit
Power on Reset
Power Down Reset
Working Register
ALU
Status Register
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
2 of 11
2005/6 Ver.1.6
MDT10P41A1
6. Pin Function Description
Pin Name
PA0
PA1~PA3
I/O
I/O
I/O
Function Description
Open drain ouput pin with 130K ohm pull-high resistor for input.
Port A, TTL input level.
PA1-PA3 are I/O pins with 50K ohm pull-high resistor for input.
PB0
PB1
PB2~PB3
I/O
I/O
I/O
I/O pin with 10K ohm pull-high resistor for input.
Open drain output with 10K ohm pull-high resistor for input.
Port B, TTL input level.
PB2-PB3 are I/O pins with 35K ohm pull-low resistors for input.
PB4~PB7
Vdd
Vss
I/O
Port B, TTL input level
Power supply
Ground
7. Memory Map
(A) Register Map
Address
00
01
02
03
04
05
06
07~1F
Description
Indirect Addressing Register
Unimplemented
PC
STATUS
MSR
Port A
Port B
Internal RAM, General Purpose Register
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
3 of 11
2005/6 Ver.1.6
MDT10P41A1
(1) IAR ( Indirect Address Register) : R0
(2) PC (Program Counter) : R2
Write PC, CALL --- always 0
LJUMP, JUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5 (ROM 1K)
LJUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
Write PC --- from ALU
LJUMP, JUMP, LCALL, CALL --- from instruction word
RTWI, RET --- from STACK
(3) STATUS (Status register) : R3
Bit
0
1
2
3
4
5
Symbol
C
HC
Z
PF
——
page 0
Carry bit
Half Carry bit
Zero bit
Power loss Flag bit
Always read as high
Page select bit :
0 : 000H --- 1FFH
1 : 200H --- 3FFH
6—7
——
General purpose bit
Function
(4) MSR (Memory Select Register) : R4
(5) PORT A : R5
Bit 3-0 : PA0~PA3, I/O Register
6-4 : Always read as high.
7
: Always read as zero.
(6) PORT B : R6
PB7~PB0, I/O Register
(7) CPIO A, CPIO B (Control Port I/O Mode Register)
The CPIO register is “write-only”
＝“0”,
I/O pin in output mode;
＝“1”,
I/O pin in input mode.
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
4 of 11
2005/6 Ver.1.6
MDT10P41A1
(8) EPROM Option by writer programming :
Security bit
Weak Disable
Disable
Enable
The default EPROM security is weak disable.
8. Reset Condition for all Registers
Register
CPIO A
CPIO B
IAR
PC
STATUS
MSR
PORT A
PORT B
Address
－－
－－
00h
02h
03h
04h
05h
06h
Power-On Reset
1111 1111
1111 1111
－
1111 1111
0001 1xxx
111x xxxx
- 111 xxxx
xxxx xxxx
Note : “ x “＝unknown, “ – “＝unimplemented, read as “0”
9. Instruction Set
Mnemonic
Operands
NOP
SLEEP
RET
CPIO R
STWR R
LDR R, t
LDWI I
SWAPR R, t
INCR R, t
Instruction Code
010000 00000000
010000 00000010
010000 00000100
010000 00000rrr
010001 1rrrrrrr
011000 trrrrrrr
111010 iiiiiiii
010111 trrrrrrr
011001 trrrrrrr
Function
No operation
Sleep mode
Return
Control I/O port register
Store W to register
Load register
Load immediate to W
Swap halves register
Increment register
Operating
None
0→WT,
stop OSC
Stack→PC
W→CPIO r
W→R
R→t
I→W
[R(0~3)
↔
R(4~7)]→t
R + 1→t
Status
TF, PF
None
None
None
Z
None
None
Z
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
5 of 11
2005/6 Ver.1.6
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