MDT10P65
1. General Description
This OTP-Based 8-bit micro-controller
uses a fully static CMOS technology
process to achieve higher speed and
smaller size with the low power
consumption and high noise immunity. On
chip memory includes 4K words of
EPROM, and 192 bytes of static RAM.
3. Applications
The application areas of this MDT10P65
range from appliance motor control and high
speed automotive to low power remote
transmitters/receivers
and
telecommunications processors, such as
Remote controller, small instruments, toy,
automobile and keyboard … etc.
2. Features
RISC CPU
Fully static design
37 single word instructions
4K x 14 program memory.
192 bytes RAM for data
35 bi-directional I/O
Eight level hardware stacks
Watchdog timer with on-chip RC
oscillator.
Interrupt capability
Timer0 : 8-bit timer with 8-bit
prescaler
Timer1 : 8-bit timer with 8-bit compare
register. This timer can be used as
carrier generator.
Sleep mode for power saving.
PB and PD with port change wake-up
interrupt.
PS : timer1 counter PC0 clock in low to high
the counter data increase
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P.1
2005/10 Ver1.6
MDT10P65
4. Pin Diagram
MDT10P65A3P/S 18 pin DIP/SOP
MDT10P65SD42 pin Shrink PDIP
PA6 1
42 PA7
/RES 2
41 PB7
PA0 3
40 PB6
PA1 4
39 PB5
PA2 5
38 PB4
PA3 6
37 PB3
PA4/T0CLK 7
36 PB2
PA5 8
35 PB1
PE0 9
34 PB0/IRQ
PE1 10
33 VDD
PE2 11
32 VSS
VDD 12
31 PD7
VSS 13
30 PD6
OSC1 14
29 PD5
OSC2 15
28 PD4
PC0/T1OSCO 16
27 PC7
PC1/T1OSCI 17
26 PC6
PC2 18
25 PC5
PC3 19
24 PC4
PD0 20
23 PD3
PD1 21
22 PD2
MDT10P65A2Q
/RES
PA2
PA3
PA4
VSS
OSC1
OSC2
PC0/T1OSCO
PC1/T1OSCI
MDT10P65A1Q
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PB4
PB3
PB2
PB1
PB0
VDD
PC7
PC6
PC5
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P.2
2005/10 Ver1.6
MDT10P65
MDT10P65 pin 28 PDIP/SOP
5. Pin function description
Pin name
OSC1
OSC2
/RES(MCLRB)
Type Buffer type
I
O
I
Description
Oscillator input
Oscillator out
Reset input with 130K ohm pull-up
Bi-directional I/O port A. Port A can be software
programmed for internal 45K ohm pull-up on all pins
except PA5. The pull-up resistance on PA5 is 100K ohm.
ST
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
TTL
TTL
TTL
Can be clock input to Timer0.
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 3
2005/10
Ver. 1.6
MDT10P65
Pin name Type Buffer type
Description
Bi-directional I/O port B. Port B can be software
programmed for internal 25K ohm pull-up on all pins.
PB0-PB7 can generate interrupt on pin state change.
Can be the external interrupt pin.
PB0/IQR
PB1
PB2
PB3
PB4
PB5
PB6
PB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0-PD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
Bi-directional I/O port C. Port C can be software
programmed for internal 100K pull-up on all pins.
Can be Timer1 oscillator output or Timer1 clock input.
Can be Timer1 oscillator input.
Bi-directional port. All pins can generate interrupt on pin
state change. Port D can be software programmed for
internal 100K pull-up on all pins.
Bi-directional port E. Port E can be software programmed
for internal 100K pull-up on all pins.
PE0
PE1
PE2
Vdd
Vss
I/O
I/O
I/O
ST
ST
ST
Power input
Ground pin
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 4
2005/10
Ver. 1.6
MDT10P65
6. Memory Mapping
6.1Program memory :
0000h
0001h
0002h
0003h
0004h
0005h
Program memory
(Page 0)
07FFh
0800h
Program memory
(Page 1)
0FFFh
Reset Vector
6.2Register file map :
BANK 0
IAR
RTCC
PCL
STATUS
MSR
PORT A
PORT B
PORT C
PORT D
PORT E
PCH
INTS
PIFB1
PIFB2
TMR1L
BANK 1
IAR
TMR
PCL
STATUS
MSR
CPIO A
CPIO B
CPIO C
CPIO D
CPIO E
PCH
INTS
PIEB1
PIEB2
PSTA
PPHE
Peripheral interrupt
Vector
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
T1STA
11h
12h
13h
14h
15h
CCP1L
16h
17h CCP1CTL
18h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
1Fh
20h
General
Purpose
Register
7Fh
General
Purpose
Register
9Fh
A0h
FFh
Unimplemented memory location.
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 5
2005/10
Ver. 1.6
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
