IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
256K x 72, 512K x 36 and 1M x 18
18Mb, PIPELINE 'NO WAIT' STATE
BUS SRAM
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
•
CKE
pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball
PBGA and 209-ball (x72) PBGA packages
• Power supply:
NVP: V
DD
2.5V (± 5%), V
DDQ
2.5V (± 5%)
NLP: V
DD
3.3V (± 5%), V
DDQ
3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
ISSI
ADVANCE INFORMATION
DECEMBER 2002
®
DESCRIPTION
The 18 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 256K words by 72 bits, 512K words
by 36 bits and 1M words by 18 bits, fabricated with
ISSI
's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable,
CKE
is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when
WE
is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-250
2.6
4
250
-200
3.1
5
200
Units
ns
ns
MHz
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
12/11/02
1
IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
ISSI
®
Bottom View
165-Ball, 13 mm x 15mm BGA
1 mm Ball Pitch, 11 x 15 Ball Array
Bottom View
209-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 11 x 19 Ball Array
Bottom View
119-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 7 x 17 Ball Array
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
12/11/02
3
IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
PIN CONFIGURATION — 256K X 72, 209-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
A
BWc
BWh
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CLK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TMS
CE2
BWg
BWd
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
A
NC
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
A
A
ADV
WE
CE
OE
V
DD
NC
NC
NC
NC
CKE
NC
NC
NC
ZZ
V
DD
MODE
A
A1
A0
A
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
A
A
CE2
BWb
BWe
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
ISSI
9
A
BWf
BWa
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
®
11 x 19 Ball BGA—14 x 22 mm
2
Body—1 mm Ball Pitch
PIN DESCRIPTIONS
Symbol
A
A0, A1
Pin Name
Synchronous Address Inputs
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Clock
Clock Enable
Synchronous Data Input/Output
Parity Data I/O
V
SS
MODE
OE
TCK, TDI
TDO, TMS
V
DD
V
DDQ
WE
ZZ
Ground
Burst Sequence Selection
Output Enable
JTAG Pins
3.3V/2.5V Power Supply
Isolated Output Buffer Supply:
3.3V/2.5V
Write Enable
Snooze Enable
ADV
BWa-BWh
CLK
CKE
DQx
DQPx
4
CE, CE2,
CE2 Synchronous Chip Enable
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
12/11/02
IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
PIN CONFIGURATION — 512K
X
36, 165-Ball PBGA (TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
NC
NC
NC
3
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BWc
BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
6
CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
7
CKE
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
8
ADV
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
ISSI
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
®
Note:
A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx
(x=a-d)
OE
ZZ
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
Output Enable
Power Sleep Mode
V
SS
MODE
TCK, TDI
TDO, TMS
V
DD
NC
DQx
DQPx
V
DDQ
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00A
12/11/02
5
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