Si5391 Data Sheet
Ultra Low-Jitter, 12-Output, Any-Frequency, Any-Output Clock
Generator
The any-frequency, any-output Si5391 clock generators combine a wide-band PLL with
proprietary MultiSynth
™
fractional synthesizer technology to offer a versatile and high
performance clock generator platform. This highly flexible architecture is capable of
synthesizing a wide range of integer and non-integer related frequencies up to 1 GHz
on 12 differential clock outputs while delivering sub-100 fs rms phase jitter performance
optimized for 100G/200G/400G applications. Each of the clock outputs can be as-
signed its own format and output voltage enabling the Si5391 to replace multiple clock
ICs and oscillators with a single device making it a true "clock tree on a chip."
The Si5391 can be quickly and easily configured using ClockBuilderPro software. Cus-
tom part numbers are automatically assigned using
ClockBuilder Pro
™
for fast, free,
and easy factory pre-programming or the Si5391 can be programmed via I2C and SPI
serial interfaces.
KEY FEATURES
• Generates any combination of output
frequencies from any input frequency
• Ultra-low jitter performance
• 69fs RMS (Precision Calibration)
• 75fs RMS (integer mode)
• 115fs RMS (fractional mode)
• Input frequency range:
• External crystal: 25 to 54 MHz
• Differential clock: 10 to 750 MHz
• LVCMOS clock: 10 to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Highly configurable outputs compatible with
LVDS, LVPECL, LVCMOS, CML, and HCSL
with programmable signal amplitude
• Si5391: 4 input, 12 output, 64-QFN 9x9mm
Applications:
• 100/200/400G switches
• 56G/112G PAM4 SerDes reference clocks
• Clock tree generation replacing XOs, buffers, signal format translators
• Clocking for FPGAs, processors, memory
• Ethernet switches/routers
• OTN framers/mappers/processors
25-54 MHz XTAL
XA
OSC
IN0
IN1
IN2
÷INT
÷INT
÷INT
PLL
XB
MultiSynth
MultiSynth
MultiSynth
MultiSynth
MultiSynth
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
Zero Delay
OUT0
OUT0A
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT9A
FB_IN
Status Flags
I2C / SPI
÷INT
Status Monitor
Control
NVM
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
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Rev. 0.7
Si5391 Data Sheet
Features List
1. Features List
The Si5391 features are listed below:
• Generates any combination of output frequencies from any in-
put frequency
• Ultra-low phase jitter performance
• 69fs RMS (Precision Calibration)
• 75fs RMS (integer mode)
• 115fs RMS (fractional mode)
• Input frequency range:
• External crystal: 25 to 54 MHz
• Differential clock: 10 to 750 MHz
• LVCMOS clock: 10 to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 1028 MHz
• LVCMOS: 100 Hz to 250 MHz
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal ampli-
tude
• Optional zero delay mode
• Glitchless on the fly output frequency changes
• DCO mode: as low as 0.001 ppb steps
• Core voltage
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output clock supply pins
• 3.3 V, 2.5 V, or 1.8 V
• Serial interface: I2C or SPI
• In-circuit programmable with non-volatile OTP memory
• ClockBuilder Pro software simplifies device configuration
• 64-QFN 9x9mm
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
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Rev. 0.7 | 2
Si5391 Data Sheet
Related Documents
2. Related Documents
Document/Resource
Si5391 Family Reference Manual
Crystal Reference Manual
Si5391A-A-EVB User Guide
Si5391P-A-EVB User Guide
Quality and Reliability
Development Kits
ClockBuilder Pro (CBPro) Software
Description/URL
https://www.silabs.com/documents/public/reference-manuals/si5391-reference-man-
ual.pdf
https://www.silabs.com/documents/public/reference-manuals/si534x-8x-recommended-
crystals-rm.pdf
https://www.silabs.com/documents/public/user-guides/ug334-si5391-evb.pdf
https://www.silabs.com/documents/public/user-guides/ug334-si5391-evb.pdf
http://www.silabs.com/quality
https://www.silabs.com/products/development-tools/timing/clock#highperformance
https://www.silabs.com/products/development-tools/software/clockbuilder-pro-software
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Rev. 0.7 | 3
Si5391 Data Sheet
Ordering Guide
3. Ordering Guide
Table 3.1. Si5391 Ordering Guide
Ordering Part Num-
ber (OPN)
Si5391A-A-GM
1, 2
Si5391B-A-GM
1, 2
Si5391C-A-GM
1, 2
Si5391D-A-GM
1, 2
Si5391P-A-EGM
Si5391A-A-EVB
Si5391P-A-EVB
Crystal / 12
4 / 12
Crystal /12
Number of Input/
Output Clocks
4/12
Output clock fre-
quency range
(MHz)
0.001 to 1028
0.001 to 350
0.001 to 1028
0.001 to 350
312.5/156.25/100/50 Precision Calibration
/25
Any-Frequency, Any Integer and Fraction-
Output
al
Evaluation Board
(A/B/C/D Grades)
Frequency Synthe-
sis Mode
Integer and Fraction-
al
Integer Only
Package
Temperature
Range
-40 to 85C
64-QFN 9x9mm
Ultra low jitter clocks Precision Calibration Evaluation Board (P
for 56G/112G
Grade)
SerDes
Note:
1. Add an R at the end of the OPN to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by Silicon Labs and the ClockBuild-
er Pro software utility. Custom part number format is: e.g., Si5391A-Axxxxx-GM, where "xxxxx" is a unique numerical sequence
representing the preprogrammed configuration.
Si5391g-Rxxxxx-GM
Timing product family
f = Multi-PLL clock
family
member (7, 6)
g = Device
grade
(A, B, C, D, P)
Product
Revision
(A)*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40 °C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Figure 3.1. Ordering Part Number Fields
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Rev. 0.7 | 4
Table of Contents
1. Features List
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Power-up and Initialization
4.2 Frequency Configuration .
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. 7
. 7
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. 8
. 9
.10
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.11
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.12
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.12
.13
.13
.13
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.13
.13
.14
.14
.14
.15
.15
.15
.15
4.3 Inputs . . . . . . . . . . . . .
4.3.1 XA/XB Clock and Crystal Input . . .
4.3.2 Input Clocks (IN0, IN1, IN2) . . . .
4.3.3 Input Selection (IN0, IN1, IN2, XA/XB)
4.4 Fault Monitoring . . . .
4.4.1 Status Indicators . .
4.4.2 Interrupt Pin (INTRb)
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4.5 Outputs . . . . . . . . . . . . . . . . . . . . .
4.5.1 Grade A/B/C/D . . . . . . . . . . . . . . . .
4.5.2 Grade P . . . . . . . . . . . . . . . . . . .
4.5.3 Output Signal Format . . . . . . . . . . . . . .
4.5.4 Differential Output Terminations . . . . . . . . . . .
4.5.5 Programmable Common Mode Voltage for Differential Outputs
4.5.6 LVCMOS Output Terminations . . . . . . . . . . .
4.5.7 LVCMOS Output Impedance and Drive Strength Selection. .
4.5.8 LVCMOS Output Signal Swing . . . . . . . . . . .
4.5.9 LVCMOS Output Polarity . . . . . . . . . . . . .
4.5.10 Output Enable/Disable . . . . . . . . . . . . .
4.5.11 Output Driver State When Disabled . . . . . . . . .
4.5.12 Synchronous/Asynchronous Output Disable Feature . . .
4.5.13 Zero Delay Mode (Grade A/B/C/D) . . . . . . . . .
4.5.14 Output Crosspoint . . . . . . . . . . . . . . .
4.5.15 Digitally Controlled Oscillator (DCO) Modes . . . . . .
4.6 Power Management .
4.8 Serial Interface
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4.7 In-Circuit Programming .
4.9 Custom Factory Preprogrammed Devices
4.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-
Programmed Devices . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5. Register Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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.17
5.1 Addressing Scheme .
6. Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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