Si514
A
N Y
-F
REQUENCY
I
2
C P
R OG R A MM A B L E
X O ( 1 0 0 k H
Z
Features
TO
250 MH
Z
)
Programmable to any frequency
from 100 kHz to 250 MHz
0.026 ppb frequency tuning
resolution
Glitch suppression on OE, power
on and frequency transitions
Low jitter operation
2- to 4-week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO for power supply
noise filtering
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Industry standard 5x7, 3.2x5, and
2.5x3.2 mm packages
–40 to 85
o
C operation
Si5602
5x7mm, 3.2x5mm
2.5x3.2mm
Ordering Information:
See page 28.
Applications
All-digital PLLs
DAC+ VCXO replacement
SONET/SDH/OTN
3G-SDI/HD-SDI/SDI
Pin Assignments:
See page 27.
Datacom
Industrial automation
FPGA/ASIC clock generation
FPGA synchronization
SDA
SCL
GND
1
2
3
6
5
4
V
DD
Description
The Si514 user-programmable I
2
C XO utilizes Silicon Laboratories' advanced PLL
technology to provide any frequency from 100 kHz to 250 MHz with programming
resolution of 0.026 parts per billion. The Si514 uses a single integrated crystal and
Silicon Labs’ proprietary DSPLL synthesizer to generate any frequency across this
range using simple I
2
C commands. Ultra-fine tuning resolution replaces DACs and
VCXOs with an all-digital PLL solution that improves performance where
synchronization is necessary or in free-running reference clock applications. This
solution provides superior supply noise rejection, simplifying low jitter clock
generation in noisy environments. Crystal ESR and DLD are individually
production-tested to guarantee performance and enhance reliability.
The Si514 is factory-configurable for a wide variety of user specifications, including
startup frequency, I
2
C address, supply voltage, output format, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long lead
times and non-recurring engineering charges associated with custom frequency
oscillators.
CLK–
CLK+
Functional Block Diagram
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si514
Si514
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . . 11
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2. Programming a Small Frequency Change (sub ±1000 ppm) . . . . . . . . . . . . . . . . . . 13
3.3. Programming a Large Frequency Change (> ±1000 ppm) . . . . . . . . . . . . . . . . . . . . 14
4. All-Digital PLL Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5. User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2. Register Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1. Dual CMOS (1:2 Fanout Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
10. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
11. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
13. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
14.1. Si514 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2
Rev. 1.2
Si514
1. Electrical Specifications
Table 1. Operating Specifications
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
Supply Voltage
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
—
Typ
3.3
2.5
1.8
21
Max
3.63
2.75
1.89
26
Units
V
V
V
mA
Supply Current
I
DD
CMOS, 100 MHz,
single-ended
LVDS
(output enabled)
LVPECL
(output enabled)
HCSL
(output enabled)
Tristate
(output disabled)
—
—
—
—
–40
19
39
41
—
—
23
43
44
18
85
mA
mA
mA
mA
o
Operating Temperature
T
A
C
Table 2. Input Characteristics
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
SDA, SCL Input Voltage High
SDA, SCL Input Voltage Low
Symbol
V
IH
V
IL
Test Condition
Min
0.80 x V
DD
—
Typ
—
—
Max
—
0.20 x V
DD
Units
V
V
Rev. 1.2
3
Si514
Table 3. Output Clock Frequency Characteristics
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
Programmable
Frequency Range
Frequency
Reprogramming
Resolution
Frequency Range for
Small Frequency Change
(Continuous Glitchless
Output)
Settling time for Small
Frequency Change
Settling time for Large
Frequency Change (Out-
put Squelched during Fre-
quency Transition)
Total Stability*
Symbol
F
O
F
O
M
RES
Test Condition
CMOS, Dual CMOS
LVDS/LVPECL/HCSL
Min
0.1
0.1
—
Typ
—
—
0.026
Max
212.5
250
—
Units
MHz
MHz
ppb
From center frequency
–1000
—
+1000
ppm
<±1000 ppm from
center frequency
>±1000 ppm from
center frequency
—
—
—
—
100
10
µs
ms
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
–30
–50
–100
–20
–25
–50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+30
+50
+100
+20
+25
+50
10
40
5
60
20
ppm
ppm
ppm
ppm
ppm
ppm
ms
µs
µs
µs
µs
Temperature Stability
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
Startup Time
Disable Time
Enable Time
T
SU
T
D
T
E
Minimum V
DD
until output
frequency (F
O
) within specification
F
O
< 10 MHz
F
O
10 MHz
F
O
< 10 MHz
F
O
10 MHz
*Note:
Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and
vibration (not under operation), and 10 years aging at 40
o
C.
4
Rev. 1.2
Si514
Table 4. Output Clock Levels and Symmetry
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
CMOS Output Logic
High
CMOS Output Logic
Low
CMOS Output Logic
High Drive
Symbol
V
OH
V
OL
I
OH
Test Condition
Min
0.85 x V
DD
—
Typ
—
—
—
—
—
—
—
—
0.8
0.6
—
Max
—
0.15 x V
DD
—
—
—
—
—
—
1.2
0.9
565
Units
V
V
mA
mA
mA
mA
mA
mA
ns
ns
ps
3.3 V
2.5 V
1.8 V
–8
–6
–4
8
6
4
—
—
—
CMOS Output Logic
Low Drive
I
OL
3.3 V
2.5 V
1.8 V
CMOS Output
Rise/Fall Time
(20 to 80% V
DD
)
LVPECL/HCSL Out-
put Rise/Fall Time
(20 to 80% V
DD
)
LVDS Output Rise/Fall
Time (20 to 80% V
DD
)
LVPECL Output Com-
mon Mode
LVPECL Output Swing
LVDS Output Common
Mode
LVDS Output Swing
HCSL Output
Common Mode
HCSL Output Swing
Duty Cycle
T
R
/T
F
0.1 to 125 MHz,
C
L
= 15 pF
0.1 to 212.5 MHz,
C
L
= no load
T
R
/T
F
T
R
/T
F
V
OC
V
O
V
OC
V
O
V
OC
V
O
DC
50
to V
DD
– 2 V, single-ended
50
to V
DD
– 2 V, single-ended
100
line-line, 3.3/2.5 V
100
line-line, 1.8 V
Single-ended 100
differential
termination
50
to
ground
Single-ended
—
—
0.55
1.13
0.83
0.25
0.35
0.58
48
—
V
DD
–
1.4 V
0.8
1.23
0.92
0.35
0.38
0.73
50
800
—
0.90
1.33
1.00
0.45
0.42
0.85
52
ps
V
V
PPSE
V
V
V
PPSE
V
V
PPSE
%
Rev. 1.2
5
FPGA/CPLD
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