VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7217
Features
• 4 ANSI X3T11 Fibre Channel and IEEE
802.3z Gigabit Ethernet Compliant Trans-
ceivers
• Over 8 Gb/s Duplex Raw Data Rate
• Redundant PECL Tx Outputs and Rx Inputs
• 8B/10B Encoder/Decoder per Channel,
Optional Encoder/Decoder Bypass Operation
• “ASIC-Friendly
TM
” Timing Options for
Transmitter Parallel Input Data
• Elastic Buffers for Intra/Inter-Chip Cable
Deskewing and Channel-to-Channel Align-
ment
• Tx/Rx Rate Matching via IDLE Insertion/
Deletion
Multi-Gigabit Interconnect Chip
• Compatible with VSC7211/7212/7214
• Fast-Locking CRU: 100-Bit Clock Periods
• Received Data Aligned to Local REFCLK or to
Recovered Clock
• PECL Rx Signal Detect and Cable Equalization
• Per-Channel Serial Tx-to-Rx and Parallel Rx-to-
Tx Internal Loopback Modes
• Clock Multiplier Generates Baud Rate Clock
• Automatic Lock-to-Reference
• JTAG Boundary Scan Support for TTL I/O
• Built-In Self Test
• 3.3V Supply, 3.0W Typ, 3.5W Max.
• 256-pin, 27mm BGA Package
VSC7217 Block Diagram
TRANSMITTER
PTXEND
TD(7:0)
C/DD
WSEND
RECEIVER
LBTXD
PTXD+
PTXD-
RTXD+
RTXD-
LBEND(1:0)
RXP/RD
PRXD+
PRXD-
RRXD+
RRXD-
LBENC(1:0)
RXP/RC
PRXC+
PRXC-
RRXC+
RRXC-
LBENB(1:0)
RXP/RB
PRXB+
PRXB-
RRXB+
RRXB-
LBENA(1:0)
RXP/RA
PRXA+
PRXA-
RRXA+
RRXA-
8
D Q
8
8B/10B
10
Encode
RTXEND
PTXENC
Clk/Data
Recovery
PSDETD
RSDETD
10
8B/10B
Decode
8
3
8
Elastic
Buffer
RD(7:0)
IDLED
KCHD
ERRD
RCLKD
RCLKDN
TC(7:0)
C/DC
WSENC
8
D Q
8
LBTXC
PTXC+
PTXC-
RTXC+
RTXC-
8B/10B
10
Encode
RTXENC
PTXENB
Clk/Data
Recovery
PSDETC
RSDETC
10
8B/10B
Decode
8
3
8
Elastic
Buffer
RC7:0)
IDLEC
KCHC
ERRC
RCLKC
RCLKCN
TB(7:0)
C/DB
WSENB
8
D Q
8
LBTXB
PTXB+
PTXB-
RTXB+
RTXB-
8B/10B
10
Encode
RTXENB
PTXENA
Clk/Data
Recovery
PSDETB
RSDETB
10
8B/10B
Decode
8
3
8
Elastic
Buffer
RB(7:0)
IDLEB
KCHB
ERRB
RCLKB
RCLKBN
TA(7:0)
C/DA
WSENA
KCHAR
8
D Q
8
LBTXA
PTXA+
PTXA-
RTXA+
RTXA-
8B/10B
10
Encode
4
RTXENA
Clk/Data
Recovery
PSDETA
RSDETA
10
8B/10B
Decode
8
3
8
Elastic
Buffer
RA(7:0)
IDLEA
KCHA
ERRD
RCLKA
RCLKAN
WSI
FLOCK
Channel
Align
WSO
TBCA
TBCB
TBCC
TBCD
DUAL
REFCLKP
REFCLKN
Tx Clock
x20/x10
Clock Gen
CAP0 CAP1
REFCLK
TBERRA
TBERRB
TBERRC
TBERRD
TMODE(2:0)
RMODE(1:0)
RESETN
ENDEC
BIST
TRSTN
TMS
TDI
TCK
JTAG
Boundary
Scan
TDO
G52325-0, Rev. 3.0
6/14/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
Mutli-Gigabit Interconnect Chip
VSC7217
General Description
The VSC7217 is a quad 8-bit parallel-to-serial and serial-to-parallel transceiver chip used for high band-
width interconnection between busses, backplanes, or other subsystems. Four Fibre Channel and Gigabit Ether-
net compliant transceivers provide up to 8.32Gb/s of duplex raw data transfer. Each channel can be operated at
a maximum data transfer rate of 1088Mb/s (8 bits at 136MHz) or a minimum rate of 784Mb/s (8 bits at
98MHz). For the entire chip in duplex mode, the aggregate transfer rate is between 6.3Gb/s and 8.7Gb/s. The
VSC7217 contains four 8B/10B encoders, serializers, de-serializers, 8B/10B decoders and elastic buffers which
provide the user with a simple interface for transferring data serially and recovering it on the receive side. The
device can also be configured to operate as four non-encoded 10-bit transceivers.
Notation
In this document, each of the four channels are identified as channel A, B, C or D. When discussing a signal
on any specific channel, the signal will have the channel letter embedded in the name: TA(7:0). When referring
to the common behavior of a signal which is used on each of the four channels, a lower case “n” is used in the
signal name: Tn(7:0). Differential signals, such as PTXA+ and PTXA-, may be referred to as a single signal,
PTXA, by dropping reference to the “+” and “-”. REFCLK refers either to the PECL/TTL input pair REF-
CLKP/REFCLKN, which can be differential PECL (using both REFCLKP and REFCLKN) or single-ended
TTL (using REFCLKP and leaving REFCLKN open).
Clock Synthesizer
Depending on the state of the
DUAL
input, the VSC7217 clock synthesizer multiplies the reference fre-
quency provided on the
REFCLK
input by 10 (DUAL is LOW) or 20 (DUAL is HIGH) to achieve a baud rate
clock between 0.98GHz and 1.36 GHz. The on-chip Phase Lock Loop (PLL) uses a single external 0.1
µ
F
capacitor, connected between CAP0 and CAP1, to control the Loop Filter. This capacitor should be a multilayer
ceramic dielectric, or better, with at least a 5V working voltage rating and a good temperature coefficient. NPO
is preferred but X7R may be acceptable. These capacitors are used to minimize the impact of common mode
noise on the Clock Multiplier Unit, especially power supply noise. Higher value capacitors provide better
robustness in systems. NPO is preferred because if an X7R capacitor is used, the power supply noise sensitivity
will vary with temperature. For best noise immunity, the designer may use a three capacitor circuit with one dif-
ferential capacitor between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from
CAP1 to ground, C3 (Figure 1). Larger values are better but 0.1
µ
F is adequate. However, if the designer cannot
use a three capacitor circuit, a single differential capacitor, C1, is adequate. These components should be iso-
lated from noisy traces.
Figure 1: Loop Filter Capacitors (Best Circuit)
CAP0
C2
C1
C3
VSC7217
CAP1
C1=C2=C3= >0.1uF
MultiLayer Ceramic
Surface Mount
NPO (Prefered) or X7R
5V Working Voltage Rating
The
REFCLK
signal can be either single-ended TTL or differential LVPECL. If TTL, connect the TTL
input to
REFCLKP
but leave
REFCLKN
open. If LVPECL, connect the inputs to
REFCLKP
and
REF-
CLKN.
Internal biasing resistors sets the proper DC Level to V
DD
/2.
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52325-0, Rev. 3.0
6/14/00
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7217
Transmitter Functional Description
Multi-Gigabit Interconnect Chip
Transmitter Data Bus
Each VSC7217 transmit channel has an 8-bit input transmit data character,
Tn(7:0),
and two control inputs,
C/Dn
and
WSENn.
The
C/Dn
input determines whether a normal data character or a special “K-character” is
transmitted, and the
WSENn
input initiates transmission of a 16-character “Word Sync Sequence” used to align
the receive channels. These data and control inputs are clocked either on the rising edge of
REFCLK,
on the
rising edge of
TBCn,
or within the data eye formed by
TBCn.
When not using
REFCLK,
each channel uses
either its own
TBCn
input, or the
TBCA
input. The transmit interface mode is controlled by
TMODE(2:0),
as
shown in Table 1.
When used, the
TBCn
inputs must be frequency locked to
REFCLK.
No phase relationship is assumed. A
small skew buffer is provided to tolerate phase drift between
TBCn
and
REFCLK.
This buffer is recentered by
the
RESETN
input, and the total phase drift after recentering must be limited to
±
180° (where 360° is one char-
acter time). Each channel has an error output,
TBERRn,
that is asserted HIGH to indicate that the phase drift
between
TBCn
and
REFCLK
has accumulated to the point that the elastic limit of the skew buffer has been
exceeded and a transmit data character has been either dropped or duplicated. This error can not occur when
input timing is referenced to
REFCLK.
The
TBERRn
output timing is identical to the low-speed receiver out-
puts, as selected by
RMODE(1:0)
in Table 5.
Table 1: Transmit Interface Input Timing Mode
TMODE(2:0)
000
001
010
011
100
101
110
111
Input Timing Reference
REFCLK Rising Edge
Reserved
TBCA
Rising Edge
TBCn
Rising Edge
TBCA
Data Eye
TBCn
Data Eye
The following figures show the possible relationships between data and control inputs and the selected
input timing source. Figure 2 shows how
REFCLK
is used as an input timing reference. This mode of opera-
tion is used in the VSC7211 and VSC7214. Figure 3 and Figure 4 show how
TBCn
is used as an input timing
reference. When
TBCn
is used to define a data eye (see Figure 4), it functions as an additional data input that
simply toggles every cycle.
Note that the
REFCLK
and
TBCn
inputs are not used directly to clock the input data. Instead, an internal
PLL generates edges aligned with the appropriate clock. The arrows on the rising edges of these signals define
the reference edge for the internal phase detection logic. An internal clock is generated at 1/10 the serial trans-
G52325-0, Rev. 3.0
6/14/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
Mutli-Gigabit Interconnect Chip
VSC7217
mit data rate that is locked to the selected input timing source. This is an especially important when
DUAL
is
HIGH and input timing is referenced to
REFCLK,
since the falling edge is NOT used. The internal clock active
edges are placed coincident with the
REFCLK
rising edges and halfway between the
REFCLK
rising edges in
this mode.
A similar situation exists when
TBCn
is used to define a data eye. Only the rising edges of
TBCn
are used
to define the external data timing. The internal clock active edges are placed at 90° and 270° points between
consecutive
TBCn
rising edges (which are assumed to be 360° apart).
Figure 2: Transmit Timing,
TMODE(2:0)
= 000
REFCLK
(DUAL = 0)
REFCLK
(DUAL = 1)
Tn(7:0)
C/Dn
WSENn
Valid
Valid
Valid
Figure 3: Transmit Timing,
TMODE(2:0)
= 10X
TBCA
or
TBCn
Tn(7:0)
C/Dn
WSENn
Valid
Valid
Valid
Figure 4: Transmit Timing,
TMODE(2:0)
= 11X (“ASIC-Friendly” Timing
0
o
90
o
180
o
270
o
360
o
TBCA or TBCn
Tn(7:0)
C/Dn
WSENn
Valid
Valid
Valid
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52325-0, Rev. 3.0
6/14/00
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC7217
Multi-Gigabit Interconnect Chip
8B/10B Encoder
Each channel contains an 8B/10B encoder which translates the 8-bit input data on
Tn(7:0)
into a 10-bit
encoded data character.
C/Dn
inputs are also provided in each channel which, along with
KCHAR,
allow the
transmission of special Fibre Channel Kxx.x characters (see Table 2). Note that
KCHAR
is a static input, and
does NOT have the same input timing as
Tn(7:0), C/Dn
and
WSENn.
Normally,
C/Dn
is LOW in order to
transmit data. If
C/Dn
is HIGH and
KCHAR
is LOW, a Fibre Channel defined IDLE Character (K28.5 =
‘0011111010’ or ‘1100000101’ depending on disparity) is transmitted and
Tn(7:0)
is ignored. If
C/Dn
is HIGH
and
KCHAR
is HIGH, a Kxx.x character is transmitted as determined by the data pattern on
Tn(7:0).
See
Table 3. Data patterns other than those defined in Table 3 produce undefined 10B encodings.
Table 2: Transmit Data Controls
WSENn
0
0
0
1
C/Dn
0
1
1
X
KCHAR
X
0
1
X
Encoded 10-bit Output
Data Character
IDLE Character (K28.5)
Special Kxx.x Character
16-Character Word Sync Sequence
Table 3: Special Characters (Selected when C/Dn and KCHAR are HIGH)
Code
K28.0
K28.1
K28.2
K28.3
K28.4
K28.5
K28.5+
Tn(7:0)
000 11100
001 11100
010 11100
011 11100
100 11100
101 11100
101 01100
Comment
User Defined
User Defined
User Defined
User Defined
User Defined
IDLE
User Defined
Code
K28.5-
K28.6
K28.7
K23.7
K27.7
K29.7
K30.7
Tn(7:0)
101 01101
110 11100
111 11100
111 10111
111 11011
111 11101
111 11110
Comment
User Defined
User Defined
Test Only
User Defined
User Defined
User Defined
User Defined
Encoder Bypass Mode
When
ENDEC
is LOW, the 8B/10B encoders are bypassed and a 10-bit input character
Tn(7:0)
is serial-
ized directly in each channel, with bit
Tn0
transmitted first. The
C/Dn
input becomes
Tn8
and
WSENn
becomes
Tn9.
The
KCHAR
input becomes
ENCDET
which is not used in the transmitter but, when HIGH,
enables Comma detection in all four receivers. Refer to the “Decoder Bypass Mode” section for a description of
this mode of operation in the receiver. The latency through the transmitter is reduced by one character time
when
ENDEC
is LOW. This mode of operation is similar to a 10-bit interface commonly found in serializer/
deserializers for the Fibre Channel (VSC7125) and Gigabit Ethernet (VSC7135) markets.
Word Sync Generation
The VSC7217 can perform channel alignment (also referred to as “word alignment” or “word sync”). In
other words, the four receive data output streams are aligned such that the same 4-byte word presented to the
G52325-0, Rev. 3.0
6/14/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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