NT6868A
Keyboard Controller
Features
n
n
n
n
n
Built-in 6502 8-bit CPU
2 MHz CPU operation frequency
4K bytes of ROM
128 bytes of SRAM
One 8-bit programmable base timer with
1 - 256
µsec
interval
n
29 programmable bi-directional I/O pins
n
3 LED direct sink pins with internal serial resistors
n
Mask optional for built-in RC oscillator with an
external resistor or external ceramic resonator applied
n
Watch-dog timer
n
Built-in power-on reset
n
Built-in low voltage reset
n
CMOS technology for low power consumption
n
Available in 40 pin DIP package and 40 pad CHIP
FORM
General Description
NT6868A is a single chip micro-controller for keyboard
applications. It incorporates a 6502 8-bit CPU core, 4K
bytes of ROM, and 128 bytes of RAM used as working
RAM and stack area. It also includes 29 programmable
bi-directional I/O pins and one 8-bit pre-loadable base
timer. Additionally, it includes a built-in low voltage
reset, a 4MHz RC oscillator that requires only a resistor
externally applied or a 4MHz ceramic resonator, and a
watch-dog timer that prevents system standstill.
Pin Configuration
GND
NC
DATA
CLK
P30
P31
P32
P33
P34
RESET
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
OSCI
R/OSCO
V
DD
LED2
LED1
LED0
P27
P26
P25
P24
P23
P22
P21
P20
P17
P16
P15
P14
P13
P12
Pad Configuration
P
1
7
P
1
6
P
1
5
P
1
4
P
1
3
P
1
2
P
1
1
P
1
0
P
0
7
P
0
6
26
25
24
23
22
21
20
19
18
17
16
15
P05
P04
P03
P02
P01
P00
RESET
P34
P33
P32
P20
P21
P22
P23
P24
P25
P26
P27
LED0
LED1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
14
13
12
11
10
9
8
7
NT6868A
9
10
11
12
13
14
15
16
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
NT6868AH
6
P31
L
E
D
2
V
D
D
R
/
O
S
C
O
O
S
C
I
G
N
D
N
C
D
A
T
A
C
L
K
P
3
0
1
V2.1
NT6868A
Block Diagram
CLK
TIMING GENERATOR
(RC OSC/CERAMIC RESONATOR:
4MHz)
4K BYTES
ROM
DATA
LED0
LED1
6502
CPU
128 BYTES
SRAM + STACK
LED2
I/O PORTS
P00 - P07
INT. CONTROLLER
WATCH DOG
TIMER
P10 - P17
P20 - P27
RESET
V
DD
GND
POWER-ON RESET/
LOW VOLTAGE RESET
BASE TIMER
P30 - P34
Pin and Pad Descriptions
Pin No.
1
2
3
4
5 - 9,
11 - 34
10
35 - 37
38
39
40
Pad No.
1
2
3
4
5 - 9,
11 - 34
10
35 - 37
38
39
40
Designation
GND
NC
DATA
CLK
P30 - P34,
P00 - P27
RESET
I/O
P
-
I/O
I/O
I/O
I
O
P
I
-
Ground pin
Description
No connection, recommended to connect V
DD
or floating
I/O, 10KΩ pull-up resistor for communication
I/O, 10KΩ pull-up resistor for communication
Bi-directional I/O pins
RESET
signal input pin with internal pull up resistor; Active low
LED0 -
LED2
V
DD
R/OSCO
OSCI
LED direct sink pins
Power supply
47KΩ resistor connected for RC OSC or 4MHz ceramic resonator
connected
No connection for RC OSC, connected for 4MHz ceramic
resonator
* Under the constraint of the maximum frequency variation, (∆F/F)
max
,
≤ ±1%,
code 3 (ceramic resonator option) must be
selected and pin 39 and pin 40 are connected to a ceramic resonator. If (∆F/F)
max
,
≤ ±10%,
code 1 (RC OSC option) is
recommended to be selected and pin39 connects a 47KΩ resistor with,
≤ ±1%
accuracy to V
DD
and pin 40 is floating.
2
NT6868A
Functional Description
6502 CPU
6502 is an 8-bit CPU. Refer to 6502 data sheet for details.
7
ACCUMULATOR A
7
INDEX REGISTER X
0
0000
SRAM
0
007F
UNUSED
00C0
0
INDEX REGISTER Y
SYSTEM REGISTERS
00CF
STACK PTR
7
15
PROGRAM COUNTER PC
7
S
7
S
V
B
D
I
Z
0
UNUSED
0
STACK POINTER SP
0
C
STATUS REGISTER P
F000
USER ROM
FFFA
CARRY
FFFB
ZERO
INTERRUPT MASK
DECIMAL MODE
BREAK
OVERFOLW
SIGN
FFFC
RST-L
FFFD
RST-H
FFFE
IRQ-L
FFFF
IRQ-H
IRQ VECTOR
NMI-H
NMI-L
NMI VECTOR
Figure 1. 6502 CPU Registers and Status Flags
Figure 2. NT6868A Memory Map
3
NT6868A
System Reserved Registers
Address
$00C0
$00C1
$00C2
$00C3
$00C4
$00C5
$00C6
$00C7
$00C8
$00C9
$00CA
$00CB
$00CC
$00CD
$00CE
$00CF
- : no effect
Register
BT
TCON
CLRIRQX
PORT0
PORT1
PORT2
PORT3
CLK
DATA
LED
CLRWDT
X
X
X
X
X
Bit7
BT7
-
-
PD07
PD17
PD27
-
-
-
-
0
X
X
X
X
X
Bit6
BT6
-
-
PD06
PD16
PD26
-
-
-
-
1
X
X
X
X
X
Bit5
BT5
-
-
PD05
PD15
PD25
-
-
-
-
0
X
X
X
X
X
Bit4
BT4
-
-
PD04
PD14
PD24
PD34
-
-
-
1
X
X
X
X
X
Bit3
BT3
-
-
PD03
PD13
PD23
PD33
-
-
-
0
X
X
X
X
X
Bit2
BT2
-
-
PD02
PD12
PD22
PD32
-
-
LED2
1
X
X
X
X
X
Bit1
BT1
-
-
PD01
PD11
PD21
PD31
-
-
LED1
0
X
X
X
X
X
Bit0
BT0
ENBT
W
W
W
RW
RW
RW
RW
RW
RW
W
W
X
X
X
X
X
CLRIRQTMR
PD00
PD10
PD20
PD30
CLK
DATA
LED0
1
X
X
X
X
X
X : access not allowed
4K X 8 ROM
The built-in ROM program code, executed by the 6502
CPU, has a capacity of 4K X 8 bits and is addressed
from F000H to FFFFH.
Power-On Reset
Built-in power-on reset circuit can generate a 150ms
pulse to reset the entire chip. The beginning of the
150ms pulse occurs at 60% of V
DD
when powered on.
128 X 8 SRAM
The built-in SRAM is used for general purpose data
memory and for the stack area. SRAM is addressed from
0000H to 007FH. User can allocate stack area in the
SRAM by setting stack pointer register (S). Because the
6502C default stack pointer is 01FFH, it must be
mapped to 007FH. Mapping from 01XX to 00XX is done
internally by setting the S register to 7FH via software
programming.
For example :
LDX
TXS
#$7F
power
V
DD
60%
The start of 150ms pulse
t
4
NT6868A
Timing Generation
This block generates the system timing and control
signal supplied to CPU and on-chip peripherals. There
are two types of system clock sources: built-in RC
oscillator or external ceramic resonator. Both of them are
mask optional and generate a 4MHz system clock. They
also generates 2MHz for CPU, and 1MHz for base timer.
The following shows the relationship of code type
number and oscillation type.
Oscillator Type
RC OSC
Ceramic Resonator
Code Number
1
3
The following table provides the relationship between
external resistor and RC OSC frequency. (for reference
only)
External Resistor
(KΩ )
39
43
47
56
RC OSC Frequency (MHz)
4.7
4.44
4
3.68
Base Timer
The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by CPU. After reset,
the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any time.
When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a timer
interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and
begin counting at 00H. The timer interval can be programmed from 1 - 256
µsec.
The base timer can be enabled by writing
a '0' to '
ENBT
' in the TCON (Timer Control) register. The
ENBT
is a level trigger.
Base timer structure:
8-Bit timer
1µs
BT pre-load data:
Addr.
$00C0
Timer Control Regisrer:
$00C1
TCON
-
-
-
-
-
-
-
ENBT
BT7
BT6
BT5
BT4
BT2
BT2
BT1
BT0
TMRINT
Bit
BT
7
BT7
6
BT6
5
BT5
4
BT4
3
BT3
2
BT2
1
BT1
0
BT0
(W)
(W)
INT. Controller
When BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by
software. Once set by an interrupt source, it remains High unless cleared by writing '1' to the corresponding bit in
CLRIRQX ($00C2H). This register is cleared to '0' on initialization by system reset.
When an interrupt occurs, CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine. When BASE TIMER
interrupt occurs and enters the interrupt service routine, the IRQTMR flag must be cleared by software.
Interrupt Control Register:
Addr.
$00C2
Bit
CLRIRQX
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
CLRIRQTMR
(W)
5
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