CXG1166AER
High Power 3
×
5 Antenna Switch MMIC with Integrated Control Logic
Description
The CXG1166AER is a high power antenna switch
MMIC for PDC handsets. There are two modes which
are TDMA mode and Packet mode.
The CXG1166AER is suited to connect Tx/Rx/
Duplexer to one of 4 antennas. This switch has on-
chip logic circuit for operation with 4 CMOS inputs.
The Sony Junction-gate PHEMT (JPHEMT) process
is used for low insertion loss and low voltage
operation.
Features
•
Low insertion loss: 0.7dB @1.44GHz
•
Low loss bypass mode in TDMA
•
High linearity: Harmonic < – 60dBc
•
CMOS compatible input control
•
Small package: 24-pin VQFN (3.3mm
×
3.3mm)
Applications
3
×
5 antenna switch for digital cellular such as PDC handsets
Structure
GaAs Junction-gate PHEMT
Absolute Maximum Ratings
(Ta = 25°C)
•
Bias voltage
V
DD
•
Control voltage
•
Operating temperature
•
Storage temperature
Vctl
Topr
Tstg
24 pin VQFN (Plastic)
7
5
–35 to +85
–65 to +150
V
V
°C
°C
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E04Y19
CXG1166AER
Block Diagram
F13
Tx
F15
Dup_In
F16
GND3
Dup_Out
F4
F17
F5
GND4
GND1
F10
F3
Ant
F14
F9
F1
Ext
F2
F6
F7
Rx
F18
F11
D_Ant
F8
D_Ext
F12
–2–
CXG1166AER
Pin Configuration/Recommended Circuit
GND1
Ant
8
7
6
C
RF
(100pF)
14
5
GND
Ext
C
RF
(100pF)
Tx
12
Dup_In
C
RF
(100pF)
GND3
Z3
13
11
10
9
GND
15
C
RF
(100pF)
GND
GND
Z1
GND
4
C
RF
(100pF)
D_Ext
GND4
Z4
16
3
GND
Dup_Out
C
RF
(100pF)
GND
17
2
C
RF
(100pF)
D_Ant
18
19
20
21
22
23
24
1
GND
C
RF
(100pF)
Cbypass
(100pF)
Cbypass
(100pF)
CTLD
V
DD
Cbypass
(100pF)
Cbypass
(100pF)
When using this IC, the following external components should be used:
This capacitor is used for RF decoupling and must be used for all applications.
C
RF
:
100pF is recommended.
Cbypass: This capacitor is used for DC line filtering. 100pF is recommended.
Rx
–3–
CTLC
CTLA
CTLB
Cbypass
(100pF)
CXG1166AER
Truth Table
A: Rx/Tx
B: Main/diversity
C: External/antenna
D: TDMA/28.8k
State
1
2
3
4
5
6
7
On Pass
Tx – Ext
Tx – Ant
Rx – Ext
Rx – Ant
Rx – D_Ext
Rx – D_Ant
Dup_Out – Ant
Rx – Ant
8
Dup_Out – Ant
Rx – D_Ant
9
Dup_Out – Ext
Rx – Ext
10
Dup_Out – Ext
Rx – D_Ext
—
H
L
H
L
L
H
L
—
L
L
H
L
L
H
L
—
H
H
H
L
L
L
H
A
H
H
L
L
L
L
—
B
—
—
L
L
H
H
L
C
L
H
L
H
L
H
H
D
L
L
L
L
L
L
H
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
L
L
L
L
H
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
H
L
H
H
H
H
H
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
L
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
L
L
L
L
L
L
L
H
L
H
L
L
H
L
H
H
L
L
L
H
L
L
L
L
H
H
H
L
H
H
L
L
L
L
L
L
H
L
H
H
L
L
H
H
L
L
L
DC Bias Condition
Item
V
DD
Vctl (H)
Vctl (L)
Min.
2.7
2.2
0
Typ.
3.0
3.0
Max.
3.5
3.5
0.4
(Ta = 25°C)
Unit
V
V
V
–4–
CXG1166AER
Electrical Characteristics
Item
Symbol
Port
Tx – Ext
Tx – Ant
Tx – Dup_In
Rx – Ext
Rx – Ant
Rx – D_Ext
Rx – D_Ant
Insertion loss
IL
Dup_Out – Ext
Rx – Ext
Dup_Out – Ant
Rx – Ant
Dup_Out – Ext
Rx – D_Ext
Dup_Out – Ant
Rx – D_Ant
Tx – Ext
Tx – Ant
Tx – Dup_In
Rx – Ext
Rx – Ant
Rx – D_Ext
Rx – D_Ant
Isolation
ISO.
Dup_Out – Ext
Rx – Ext
Dup_Out – Ant
Rx – Ant
Dup_Out – Ext
Rx – D_Ext
Dup_Out – Ant
Rx – D_Ant
Tx – Rx
∗
1
∗
1
∗
1
∗
2
∗
2
∗
2
∗
2
∗
1
,
∗
4
∗
2
,
∗
5
∗
1
,
∗
4
∗
2
,
∗
5
∗
1
,
∗
4
∗
2
,
∗
5
∗
1
,
∗
4
∗
2
,
∗
5
∗
1
∗
1
∗
1
∗
2
∗
2
∗
2
∗
2
∗
1
,
∗
4
∗
2
,
∗
5
∗
1
,
∗
4
∗
2
,
∗
5
∗
1
,
∗
4
∗
2
,
∗
5
∗
1
,
∗
4
∗
2
,
∗
5
∗
1
Condition
(Ta = 25°C)
Min. Typ. Max. Unit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
24
24
19
24
24
24
24
29
29
29
29
24
24
24
24
43
0.75
0.7
0.25
0.65
0.65
0.45
0.45
0.75
0.8
0.9
0.95
0.45
0.5
0.45
0.5
30
30
25
30
30
30
30
35
35
35
35
30
30
30
30
50
1.0
0.95
0.5
0.9
0.9
0.7
0.7
1.0
1.05
1.15
1.2
0.7
0.75
0.7
0.75
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
∗
1
Pin = 29.5dBm, 0/3V control, V
DD
= 2.7V to 3.5V, 1,429MHz to 1,453MHz
∗
2
Pin = 10dBm, 0/3V control, V
DD
= 2.7V to 3.5V, 1,477MHz to 1,501MHz
∗
3
π/4-shifted
DQPSK, Pin = 29.5dBm, 0/3V control, V
DD
= 3.0V, 1,429MHz to 1,453MHz,
ACP (±50kHz) < – 70dBc, ACP (±100kHz) < – 75dBc, 2nd harmonics < – 75dBc, 3rd harmonics < – 75dBc
∗
4
Rx terminal end is OPEN (Pattern cut).
∗
5
Dup_Out terminal end is OPEN (Pattern cut).
–5–