CXD2408AR
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD2408AR is an IC developed to generate
the timing pulses required by the Progressive Scan
CCD image sensors as well as signal processing
circuits.
Features
•
EIA support
•
Electronic shutter function
•
Random trigger shutter function
•
Sync signal generator
•
Supports external synchronization
•
Supports non-interlaced operation
•
Base oscillation 1560fh (24.5454MHz)
Applications
Progressive Scan CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX074AK, ICX074AL
64 pin LQFP (Plastic)
Absolute Maximum Ratings
V
•
Supply voltage
V
DD
V
SS
– 0.5 to +7.0
•
Input voltage
V
I
V
SS
– 0.5 to V
DD
+ 0.5 V
•
Output voltage
V
O
V
SS
– 0.5 to V
DD
+ 0.5 V
•
Operating temperature Topr
–20 to +75
°C
•
Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
•
Supply voltage
V
DD
4.75 to 5.25
•
Operating temperature Topr
–20 to +75
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96402A68
CXD2408AR
Block Diagram
XCPDM
XCPOB
REVH
REND
SYNC
OCTL
HDO
O2FH
PBLK
WEN
RDM
VDO
VDI
RM
CLD
BLK
EXT
HDI
FLD
47 46 45 44 43 42 41 39 38 37 36 59 58 61 60 57 54 53 51 50 49
CL
ID
RG 11
XH1 13
XH2 14
XSHP 28
XSHD 29
XRS 30
XV1 26
XV2 25
XV3 22
XSG 27
XHHG1A 15
XHHG1B 16
XHHG2 17
XVOG 18
XVHOLD 19
DECODE
1/2
COUNTER
TG
OUTPUT CONTROL
63 VRI
62 HRI
GATE
V-CONTROL
PULSE GENERATOR
H-DECODER
1/390
V-DECODER
1/525
20 TEST1
21 TEST2
31
TEST3
32 TEST4
48 TEST8
TEST CIRCUIT
35 TEST7
34 TEST6
33 TEST5
GATE
52 NC
64
1
2
8 10 3
4
5
6
7
9
12
23
24 40
55 56
SMD1
V
SS
OSCO
V
DD
CKI
V
SS
PS
V
SS
V
SS
TRIG
ED0
ED1
24.5MHz
–2–
SMD2
XSUB
OSCI
ED2
V
DD
CXD2408AR
Pin Configuration
XCPDM
XCPOB
TEST8
WEN
PBLK
RDM
REVH
RM
ID
48
CL
CLD
O2FH
NC
FLD
BLK
V
SS
V
DD
SYNC
HDI
VDI
HDO
VDO
HRI
VRI
CKI
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
47
46
45
44
43 42
41 40 39
38 37
EXT
V
SS
TEST7
36 35
34 33
32
31
30
29
28
27
26
TEST4
TEST3
XRS
XSHD
XSHP
XSG
XV1
XV2
V
DD
V
SS
XV3
TEST2
TEST1
XVHOLD
XVOG
XHHG2
TEST6
TEST5
25
24
23
22
21
20
19
18
17
16
CXD2408AR (G/A)
REND
OCTL
2
3
4
5
6
7
8
9
10
11 12
13
14 15
–3–
XHHG1A
XHHG1B
OSCO
SMD1
SMD2
XSUB
OSCI
ED1
ED0
V
SS
RG
PS
ED2
TRIG
XH1
XH2
CXD2408AR
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Symbol
OSCO
OSCI
PS
ED0
ED1
ED2
SMD1
Vss
SMD2
TRIG
RG
XSUB
XH1
XH2
XHHG1A
XHHG1B
XHHG2
XVOG
XVHOLD
TEST1
TEST2
XV3
Vss
V
DD
XV2
XV1
XSG
XSHP
XSHD
XRS
TEST3
TEST4
TEST5
TEST6
TEST7
I/O
O
I
I
I
I
I
I
—
I
I
O
O
O
O
O
O
O
O
O
O
O
O
—
—
O
O
O
O
O
O
O
O
O
O
I
Inverter output for oscillation.
Inverter input for oscillation.
Switching for electronic shutter speed input method. (With pull-down resistor)
Low: Parallel input, High: Serial input
Shutter speed setting. Strobe input for serial mode. (With pull-up resistor)
Shutter speed setting. Clock input for serial mode. (With pull-up resistor)
Shutter speed setting. Data input for serial mode. (With pull-up resistor)
Shutter mode setting. (With pull-up resistor)
GND
Shutter mode setting. (With pull-up resistor)
Trigger input for random trigger shutter.
Reset gate pulse output.
CCD discharge pulse output.
Clock output for CCD horizontal register drive.
Clock output for CCD horizontal register drive.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer between CCD horizontal registers.
Clock output for transfer from CCD vertical register to CCD horizontal register.
Clock output for adjusting timing of transfer to CCD horizontal register.
Test output. Normally open.
Test output. Normally open.
Clock output for CCD vertical register drive.
GND
Power supply.
Clock output for CCD vertical register drive.
Clock output for CCD vertical register drive.
CCD sensor charge readout pulse output.
Precharge level sample-and-hold pulse.
Data sample-and-hold pulse.
Sample-and-hold pulse.
Test output. Normally open.
Test output. Normally open.
Test output. Normally open.
Test output. Normally open.
Test input. Set at Low in normal operation. (With pull-down resistor)
–4–
Description
CXD2408AR
Pin
No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
EXT
REND
REVH
OCTL
Vss
RDM
RM
XCPDM
XCPOB
PBLK
ID
WEN
TEST8
CL
CLD
O2FH
NC
FLD
BLK
Vss
V
DD
SYNC
HDI
VDI
HDO
VDO
HRI
VRI
CKI
I/O
I
I
I
I
—
I
I
O
O
O
O
O
I
O
O
O
—
O
O
—
—
O
I
I
O
O
I
I
I
Field pulse output.
Composite blanking output.
GND
Power supply.
Composite sync output.
Horizontal sync signal input.
Vertical sync signal input.
Horizontal sync signal output.
Vertical sync signal output.
Horizontal reset signal input.
Vertical reset signal input.
2 fck clock input.
Description
Internal synchronization/external synchronization switching. (With pull-down resistor)
Low: Internal synchronization, High: External synchronization
Normal reset/direct reset switching. (With pull-down resistor)
Low: Normal reset, High: Direct reset
V reset/HV reset switching. (With pull-down resistor)
Low: V reset, High: HV reset
O2FH output control. (With pull-down resistor)
Low: No output, High: Output
GND
Normal operation/random trigger shutter switching. (With pull-down resistor)
Low: Normal operation, High: Random trigger shutter
Switching for output mode. (With pull-down resistor)
Low: Non-interlaced, High: Interlaced
Clamp pulse output.
Clamp pulse output.
Blanking cleaning pulse output.
Line identification output.
Write enable output.
Test input. (With pull-down resistor)
fck clock output. (0°)
fck clock output. (180°)
2 fH output.
–5–
创意市集
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
