74LVC16374A; 74LVCH16374A
Rev. 12 — 20 November 2018
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
Product data sheet
1. General description
The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate
D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus-
oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock
input (nCP) and an output enable (nOE) are provided for each octal.
The flip-flops store the state of their individual D-inputs that meet the set-up and hold time
requirements on the LOW-to-HIGH clock (CP) transition.
When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is
HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the
state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to
the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.
2. Features and benefits
•
•
•
•
•
•
•
•
•
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pinout architecture
Low inductance multiple supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16374A only)
High-impedance outputs when V
CC
= 0 V
Complies with JEDEC standard:
•
JESD8-7A (1.65 V to 1.95 V)
•
JESD8-5A (2.3 V to 2.7 V)
•
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-B exceeds 200 V
•
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
•
•
Nexperia
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC16374ADL
74LVC16374ADGG
74LVCH16374ADGG
-40 °C to +125 °C
-40 °C to +125 °C
Name
SSOP48
TSSOP48
Description
plastic shrink small outline package;
48 leads; body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT370-1
SOT362-1
4. Functional diagram
1
1OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1CP
48
2CP
25
001aaa253
24
2OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1
1OE
48
1CP
24
2OE
25
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
EN1
C3
EN2
C4
3D
1
2
3
5
6
8
9
11
12
4D
2
13
14
16
17
19
20
22
23
001aaa254
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
Fig. 1.
Logic symbol
1D0
D
CP
FF1
1CP
1OE
Q
1Q0
Fig. 2.
2D0
IEC logic symbol
D
CP
FF2
Q
2Q0
2CP
2OE
to 7 other channels
to 7 other channels
001aaa255
Fig. 3.
Logic diagram
74LVC_LVCH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 12 — 20 November 2018
2 / 15
Nexperia
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
V
CC
data input
to internal circuit
mna705
Fig. 4.
Bus hold circuit
5. Pinning information
5.1. Pinning
74LVC16374A
74LVCH16374A
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48 1CP
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 V
CC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 V
CC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2CP
001aaa231
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
V
CC
18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
Fig. 5.
Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
74LVC_LVCH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 12 — 20 November 2018
3 / 15
Nexperia
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5.2. Pin description
Table 2. Pin description
Symbol
1OE, 2OE
GND
V
CC
1Q0 to 1Q7
2Q0 to 2Q7
1D0 to 1D7
2D0 to 2D7
1CP, 2CP
Pin
1, 24
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
48, 25
Description
output enable input (active LOW)
ground (0 V)
supply voltage
data output
data output
data input
data input
clock input
6. Functional description
Table 3. Function selection
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state; ↑ = LOW-to-HIGH transition;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition.
Operating mode
Load and read register
Load register and disable outputs
Input
nOE
L
L
H
H
nCP
↑
↑
↑
↑
nDn
l
h
l
h
L
H
L
H
L
H
Z
Z
Internal flip-flop
Output nQ0 to nQ7
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
V
O
> V
CC
or V
O
< 0 V
output HIGH-or LOW-state
output 3-state
V
O
= 0 V to V
CC
[2]
[2]
Min
-0.5
-50
-0.5
-
-0.5
-0.5
-
-
-100
-65
Max
+6.5
-
+6.5
±50
+6.5
±50
100
-
+150
500
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
CC
+ 0.5 V
T
amb
= -40 °C to +125 °C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For (T)SSOP48 packages: above 60 °C, the value of P
tot
derates linearly with 5.5 mW/K.
74LVC_LVCH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 12 — 20 November 2018
4 / 15
Nexperia
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
Parameter
Conditions
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
active mode
power-down mode; V
CC
= 0 V
Min
1.65
1.2
0
0
0
-40
0
0
Typ
-
-
-
-
-
-
-
-
Max
3.6
-
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
V
°C
ns/V
ns/V
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
Min
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level input V
CC
= 1.2 V
voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
= -100 μA;
V
CC
= 1.65 V to 3.6 V
I
O
= -4 mA; V
CC
= 1.65 V
I
O
= -8 mA; V
CC
= 2.3 V
I
O
= -12 mA; V
CC
= 2.7 V
I
O
= -18 mA; V
CC
= 3.0 V
I
O
= -24 mA; V
CC
= 3.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 100 μA;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
I
OZ
input leakage
current
OFF-state
output current
V
CC
= 3.6 V; V
I
= 5.5 V or GND[2]
V
I
= V
IH
or V
IL
; V
CC
= 3.6 V;
V
O
= 5.5 V or GND[2]
-
-
-
-
-
-
-
0
-
-
-
-
±0.1
±0.1
0.2
0.45
0.6
0.4
0.55
±5
±5
-
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
±20
±20
V
V
V
V
V
μA
μA
V
CC
- 0.2
1.2
1.8
2.2
2.4
2.2
V
CC
-
-
-
-
-
-
-
-
-
-
-
V
CC
- 0.3
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
-
V
V
V
V
V
V
1.08
0.65xV
CC
1.7
2.0
-
-
-
-
-40 °C to +85 °C
Typ[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.12
0.35xV
CC
0.7
0.8
-40 °C to +125 °C
Min
1.08
0.65xV
CC
1.7
2.0
-
-
-
-
Max
-
-
-
-
0.12
0.7
0.8
V
V
V
V
V
V
V
Unit
0.35xV
CC
V
74LVC_LVCH16374A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 12 — 20 November 2018
5 / 15
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
