BUK9219-55A
N-channel TrenchMOS logic level FET
Rev. 02 — 7 June 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Q101 compliant
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V and 24 V loads
Automotive and general purpose
power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
V
GS
= 5 V; T
mb
= 25 °C;
see
Figure 1;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max Unit
55
55
114
V
A
W
Nexperia
BUK9219-55A
N-channel TrenchMOS logic level FET
Table 1.
Symbol
R
DSon
Quick reference data
…continued
Parameter
drain-source
on-state
resistance
Conditions
V
GS
= 4.5 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 12;
see
Figure 13
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 12;
see
Figure 13
V
GS
= 5 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 12;
see
Figure 13
Avalanche ruggedness
E
DS(AL)S
non-repetitive
I
D
= 49 A; V
sup
≤
55 V;
drain-source
R
GS
= 50
Ω;
V
GS
= 5 V;
avalanche energy T
j(init)
= 25 °C; unclamped
-
-
120
mJ
Min
-
Typ
-
Max Unit
20
mΩ
Static characteristics
-
14
17.6 mΩ
-
15
19
mΩ
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
mounting base; connected to
drain
2
1
3
mb
D
Simplified outline
Graphic symbol
G
mbb076
S
SOT428 (DPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9219-55A
DPAK
Description
plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
Version
SOT428
Type number
BUK9219-55A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 7 June 2010
2 of 14
Nexperia
BUK9219-55A
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
mb
= 100 °C; V
GS
= 5 V; see
Figure 1
T
mb
= 25 °C; V
GS
= 5 V; see
Figure 1;
see
Figure 3
I
DM
P
tot
T
stg
T
j
V
GSM
peak drain current
total power dissipation
storage temperature
junction temperature
peak gate-source
voltage
source current
peak source current
non-repetitive
drain-source
avalanche energy
pulsed; t
p
≤
50 µs
T
mb
= 25 °C; t
p
≤
10 µs; pulsed;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
R
GS
= 20 kΩ
Min
-
-
-10
-
-
-
-
-55
-55
-15
Typ
-
-
-
-
-
-
-
-
-
-
Max
55
55
10
38
55
219
114
175
175
15
Unit
V
V
V
A
A
A
W
°C
°C
V
Source-drain diode
I
S
I
SM
E
DS(AL)S
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
I
D
= 49 A; V
sup
≤
55 V; R
GS
= 50
Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
-
-
-
-
-
-
55
219
120
A
A
mJ
Avalanche ruggedness
[1]
peak drain current is limited by chip, not package.
BUK9219-55A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 7 June 2010
3 of 14
Nexperia
BUK9219-55A
N-channel TrenchMOS logic level FET
120
I
der
(%)
80
03aa24
120
P
der
(%)
80
03aa16
40
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
10
3
I
D
(A)
R
DSon
= V
DS
/ I
D
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
03nb64
10
2
t
p
= 10µs
100
µs
t
p
T
10
P
δ
=
1 ms
D.C.
10 ms
t
p
T
t
100 ms
10
V
DS
(V)
10
2
1
1
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK9219-55A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 7 June 2010
4 of 14
Nexperia
BUK9219-55A
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
Conditions
Min
-
-
Typ
-
71.4
Max
1.3
-
Unit
K/W
K/W
thermal resistance from junction to see
Figure 4
mounting base
thermal resistance from junction to minimum footprint ; FR4
ambient
board
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
10
−1
0.1
0.05
0.02
10
−2
P
03nb65
δ
=
t
p
T
Single Shot
t
p
t
T
10
−3
10
−6
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9219-55A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 02 — 7 June 2010
5 of 14
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