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74ALVCH16652DGGY: 产品描述IC TXRX NON-INVERT 3.6V 56TSSOP; 产品类别逻辑逻辑; 文件大小250KB，共18页; 制造商Nexperia; 官网地址https://www.nexperia.com

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74ALVCH16652DGGY概述

IC TXRX NON-INVERT 3.6V 56TSSOP

74ALVCH16652DGGY规格参数

参数名称	属性值
Brand Name	Nexperia
厂商名称	Nexperia
零件包装代码	TSSOP
包装说明	TSSOP,
针数	56
制造商包装代码	SOT364-1
Reach Compliance Code	compliant
Samacsys Description	74ALVCH16652 - 16-bit transceiver/register with dual enable; 3-state@en-us
其他特性	SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
系列	ALVC/VCX/A
JESD-30 代码	R-PDSO-G56
长度	14 mm
逻辑集成电路类型	REGISTERED BUS TRANSCEIVER
湿度敏感等级	2
位数	8
功能数量	2
端口数量	2
端子数量	56
最高工作温度	85 °C
最低工作温度	-40 °C
输出特性	3-STATE
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	TSSOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）	260
传播延迟（tpd）	6.8 ns
座面最大高度	1.2 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	1.2 V
标称供电电压 (Vsup)	2.4 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	GULL WING
端子节距	0.5 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
宽度	6.1 mm

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74ALVCH16652

Rev. 3 — 12 September 2018

16-bit transceiver/register with dual enable; 3-state

Product data sheet

1. General description

The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-

type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the

data bus or from the internal storage registers.

Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock

inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and nSBA) or output enable

(nOEAB and nOEBA) control inputs.

Depending on the select inputs nSAB and nSBA data can directly go from input to output (real-time

mode) or data can be controlled by the clock (storage mode), when OE inputs permit this operating

mode.

The output enable inputs nOEAB and nOEBA determine the operation mode of the transceiver.

When nOEAB is LOW, no data transmission from nBn to nAn is possible and when nOEBA is

HIGH, no data transmission from nBn to nAn is possible.

When nSAB and nSBA are in the real-time transfer mode, it is also possible to store data without

using the internal D-type flip-flops by simultaneously enabling nOEAB and nOEBA. In this

configuration each output reinforces its input.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

2. Features and benefits

•

Wide supply voltage range of 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

Current drive ±24 mA at V

= 3.0 V.

MULTIBYTE flow-through standard pin-out architecture

Low inductance multiple V

and GND pins for minimum noise and ground bounce

All data inputs have bushold

Output drive capability 50 Ω transmission lines at 85 °C

Complies with JEDEC standards:

•

JESD8-5 (2.3 V to 2.7 V)

•

JESD8B/JESD36 (2.7 V to 3.6 V)

ESD protection:

•

HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

•

CDM JESD22-C101E exceeds 1000 V

•

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

74ALVCH16652DGG −40 °C to +85 °C

TSSOP56

Description

Version

plastic thin shrink small outline package; 56 leads; SOT364-1

body width 6.1 mm

74ALVCH16652DGGY相似产品对比

	74ALVCH16652DGGY	74ALVCH16652DGGS	74ALVCH16652DGG:11
描述	IC TXRX NON-INVERT 3.6V 56TSSOP	IC TXRX NON-INVERT 3.6V 56TSSOP	74ALVCH16652 - 16-bit transceiver/register with dual enable; 3-state TSSOP 56-Pin
Brand Name	Nexperia	Nexperia	Nexperia
零件包装代码	TSSOP	TSSOP	TSSOP
包装说明	TSSOP,	TSSOP,	TSSOP,
针数	56	56	56
制造商包装代码	SOT364-1	SOT364-1	SOT364-1
其他特性	SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA	SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA	SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
系列	ALVC/VCX/A	ALVC/VCX/A	ALVC/VCX/A
JESD-30 代码	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56
长度	14 mm	14 mm	14 mm
逻辑集成电路类型	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER	REGISTERED BUS TRANSCEIVER
湿度敏感等级	2	2	1
位数	8	8	8
功能数量	2	2	2
端口数量	2	2	2
端子数量	56	56	56
最高工作温度	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C
输出特性	3-STATE	3-STATE	3-STATE
输出极性	TRUE	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSSOP	TSSOP	TSSOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）	260	260	260
传播延迟（tpd）	6.8 ns	6.8 ns	6.8 ns
座面最大高度	1.2 mm	1.2 mm	1.2 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	1.2 V	1.2 V	1.2 V
标称供电电压 (Vsup)	2.4 V	2.4 V	2.4 V
表面贴装	YES	YES	YES
技术	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子形式	GULL WING	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm	0.5 mm
端子位置	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30	30
宽度	6.1 mm	6.1 mm	6.1 mm
厂商名称	Nexperia	Nexperia	-
Reach Compliance Code	compliant	compliant	-
Samacsys Description	74ALVCH16652 - 16-bit transceiver/register with dual enable; 3-state@en-us	74ALVCH16652 - 16-bit transceiver/register with dual enable; 3-state@en-us	-

74ALVCH16652DGGY

74ALVCH16652DGGY在线购买

74ALVCH16652DGGY概述

74ALVCH16652DGGY规格参数

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