Ordering number : :ENA1869A
Ordering number ENA1951
LC87F2W48A
CMOS IC
50K-byte FROM and 1536-byte RAM integrated
8-bit 1-chip Microcontroller
Overview
http://onsemi.com
The LC87F2W48A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 50K-byte flash ROM (On-board-
programmable), 1536-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8-
bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a
prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface, an
asynchronous/synchronous SIO interface, a UART interface (full duplex), two 12-bit PWM channels, a 14-channel
AD converter with 12-/8-bit resolution selector, a system clock frequency divider, an infrared remote controller
receiver circuit, and a 24-source 10-vector interrupt feature.
Features
Flash
ROM
•
Capable of on-board-programming with wide range, 2.7 to 5.5V, of voltage source.
•
Block-erasable in 128 byte units
•
Writable in 2-byte units
•
51200
×
8 bits
RAM
•
1536
×
9 bits
Minimum
Bus Cycle
•
83.3ns (12MHz) VDD=2.7V to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.00
83111HKIM 20101027-S00001 No.A1869-1/26
LC87F2W48A
Minimum
instruction cycle time
•
250ns (12MHz) VDD=2.7 to 5.5V
Ports
•
Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1-bit units
•
Dedicated oscillator ports/input ports
•
Reset pin
•
On-chip Debugger pin
•
Power pins
38 (P0n, P1n, P2n, P31 to P36, P70 to P73,
PWM0, PWM1, XT2, CF2)
2 (XT1, CF1)
1 (RES)
1 (OWP0)
6 (VSS1 to 3, VDD1 to 3)
Timers
•
Timer 0: 16 bit timer / counter with capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
×
2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
•
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler
×
2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
•
Timer 4: 8-bit timer with a 6-bit prescaler
•
Timer 5: 8-bit timer with a 6-bit prescaler
•
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
•
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
•
Base Timer
(1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock,
and timer 0 prescaler output.
(2) Interrupts are programmable in 5 different time schemes
High-speed
Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real-time.
Serial
Interface
•
SIO 0: 8-bit synchronous serial interface
(1) LSB first/MSB first mode selectable
(2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tCYC)
(3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of
data transmission possible in 1-byte units)
•
SIO 1: 8-bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect)
No.A1869-2/26
LC87F2W48A
UART
•
Full duplex
•
7/8/9 bit data bits selectable
•
1 stop bit (2-bit in continuous data transmission)
•
Built-in baudrate generator
AD
Converter: 12 bits/8 bits
×
14 channels
•
12 bits/8 bits AD converter resolution selectable
PWM:
Multifrequency 12-bit PWM
×
2 channels
Infrared Remote Controller Receiver Circuit
1) Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is
selected as the reference clock source)
2) Supports data encording systems such as PPM (Pulse Position Modulation) and Manchester encording
3) X’tal HOLD mode release function
Clock
Output Function
•
Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the
system clock.
•
Can generate the source clock for the subclock.
Watchdog
Timer
•
External RC watchdog timer
•
Interrupt and reset signals selectable
Interrupts
•
24 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector Address
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
INT0
INT1
INT2/T0L/INT4/REMOREC2
INT3/INT5/BT0/BT1
T0H
T1L/T1H
SIO0/UART1 receive
SIO1/UART transmit
ADC/T6/T7
Port 0/T4/T5/PWM0,1
Interrupt Source
•
Priority levels X > H > L
•
Of interrupts of the same level, the one with the smallest vector address takes precedence.
•
IFLG (List of interrupt source flag function)
(1) Shows a list of interrupt source flags that caused a branching to a particular vector address
(shown in the table above.)
Subroutine
Stack Levels: 768 levels (the stack is allocated in RAM.)
High-speed
Multiplication/Division Instructions
•
16 bits
×
8 bits
(5 tCYC execution time)
•
24 bits
×
16 bits
(12 tCYC execution time)
•
16 bits
÷
8 bits
(8 tCYC execution time)
•
24 bits
÷
16 bits
(12 tCYC execution time)
No.A1869-3/26
LC87F2W48A
Oscillation
Circuits
•
Internal oscillation circuits
1) Low-speed RC oscillation circuit:
For system clock (100kHz)
2) Medium-speed RC oscillation circuit:
For system clock (1MHz)
3) Frequency variable RC oscillation circuit: For system clock (6 to 10MHz)
(1) Adjustable in
±0.5%
(typ) step from a selected center frequency.
(2) Measures oscillation clock using a input signal from XT1 as a reference.
•
External oscillation circuits
1) Low speed crystal oscillation circuit:
For low-speed system clock, with internal Rf
2) Hi-speed CF oscillation circuit:
For system clock, with internal Rf
(1) Both the CF and crystal oscillator circuits stop operation on a system reset.
System
Clock Divider function
•
Can run on low current.
•
The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs
(at a main clock rate of 10MHz).
Standby
Function
•
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Occurrence of an interrupt
•
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0
•
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except base timer
and infrared remote controller receiver circuit.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are six ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5
* INT0 and INT1 X'tal HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0
(5) Having an interrupt source established in the base timer circuit
(6) Having an interrupt source established in the infrared remote controller receiver circuit
Onchip
Debugger
•
Supports software debugging with the IC mounted on the target board.
Data
Security Function (Flash versions only)
•
Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
No.A1869-4/26
LC87F2W48A
Package
Form
•
SQFP48 (7×7) (Lead-/Halogen-free type)
Development
Tools
•
On-chip-debugger: TCB87-TypeC (1 wire version) + LC87F2W48A
Flash
ROM Programming Boards
Package
SQFP48 (7×7)
Programming boards
W87F55256SQ
Package Dimensions
unit : mm (typ)
3163B
9.0
7.0
36
37
25
24
48
1
0.5
(0.75)
12
0.18
13
7.0
9.0
0.15
1.7max
0.1
(1.5)
SANYO : SQFP48(7X7)
0.5
No.A1869-5/26
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