CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
SYMBOL
V
DD
I
DD1
I
DD2
I
DDA
V
TH1
V
TH1HYST
V
TH2
Over the recommended operating conditions unless otherwise specified.
TEST CONDITIONS
MIN
2.0
V
DD
= 5.0V
V2MON = 3.3V
V3MON = 1.0V
12.5
5.5
19
TYP
MAX
5.5
15
6
100
UNITS
V
µA
µA
nA
PARAMETER
Supply Voltage Range
V
DD
Supply Current
V2MON Input Current
V3MON Input Current
VOLTAGE THRESHOLDS
Fixed Voltage Trip Point for V
DD
Hysteresis of V
TH1
Fixed Voltage Trip Point for V2MON
ISL88021/22IU8HxZ
ISL88021/22IU8FxZ
V
TH1
= 4.64V
V
TH1
= 3.09V
ISL88021/22IU8xFZ
ISL88021/22IU8xEZ
ISL88021/22IU8xCZ
ISL88021/22IU8xAZ
V
TH2HYST
Hysteresis of V
TH2
V
TH2
= 3.09V
V
TH2
= 2.92V
V
TH2
= 2.32V
V
TH2
= 2.19V
V
TH2
= 1.69V
V
TH3
V
REFHYST
RESET
V
OL
V
OH
t
RPD
t
POR
C
LOAD
Reset Output Voltage Low
V
DD
3.3V, Sinking 2.5mA
V
DD
< 3.3V, Sinking 1.5mA
RST Output Voltage High
V
DD
3.3V, Sourcing 2.5mA
V
DD
< 3.3V, Sourcing 1.5mA
V
TH
to Reset Asserted Delay
POR Timeout Delay
Load Capacitance on Reset Pins
C
POR
is open
140
V
DD
-0.6
V
DD
-0.6
0.05
0.05
V
DD
-0.4
V
DD
-0.4
10
200
5
0.40
0.40
V
V
V
V
µs
ms
pF
V3MON Threshold Voltage
V
TH
for V3MON on ISL88021
V
TH
for V3MON on ISL88022
Hysteresis Voltage
0.594
0.587
3.034
2.894
2.290
1.660
4.565
3.029
4.649
3.085
46
37
3.090
2.947
2.332
1.690
37
29
23
22
17
0.605
0.595
3
0.616
0.603
3.146
3.000
2.374
1.720
4.733
3.141
V
V
mV
mV
V
V
V
V
mV
mV
mV
mV
mV
V
V
mV
FN8226 Rev 1.00
September 18, 2006
Page 3 of 8
ISL88021, ISL88022
Electrical Specifications
SYMBOL
MANUAL RESET
V
MRL
V
MRH
t
MR
R
PU
MR Input Voltage Low
MR Input Voltage High
MR Minimum Pulse Width
Internal Pull-Up Resistor
V
DD
-0.6
550
20
0.8
V
V
ns
k
Over the recommended operating conditions unless otherwise specified.
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETER
Functional Description
The ISL88021 and ISL88022 devices incorporate such features
as Power-On-Reset control, Supply Voltage Supervision,
Undervoltage or Overvoltage Monitoring, and Manual Reset
Assertion.
The ISL88021 and ISL88022 devices provide common preset
threshold voltages on both V
DD
and V2MON and for an optional
resistor divider network on V3MON to provide custom voltage
monitoring of voltages greater than 0.6V. An optional capacitor
can be connected between the C
POR
pin and GND to increase
the nominal 200ms t
POR
delay. Figure 7 illustrates operational
functionality with a timing diagram.
Power-On-Reset (POR)
Applying power to the ISL88021 and ISL88022 devices activates
a POR circuit which holds the RESET pin low once V
DD
> 1V.
This signal provides several benefits:
• It prevents the system microprocessor from starting to operate
with insufficient voltage.
• It prevents the processor from operating prior to
stabilization of the oscillator.
• It ensures that the monitored device is held out of operation
until internal registers are properly loaded.
• It allows time for an FPGA to download its configuration prior to
initialization of the circuit.
When all of the monitored voltages meet their respective input
voltage requirements for the specified reset timeout delay
t
POR
, the POR circuit simultaneously pulls the RST output low
and releases the RST output to allow the system to begin
operation.
Voltage Monitoring
During normal operation, the ISL88021 and ISL88022 monitor the
voltage levels on V
DD
, V2MON and V3MON. The ISL88021
asserts reset if any one of these voltages fall below their
respective voltage trip points and in the case of ISL88022 above
the voltage trip point on the V3MON input. The reset signal
effectively prevents the microprocessor from operating during a
power failure, brownout or over voltage condition. This signal
remains active until all monitored voltages meet all voltage
threshold requirements for the reset time delay period t
POR
. Note
that both RESET and RESET signals are provided for design
flexibility. Figure 1 illustrates the VDD, V2MON and V3MON input
threshold voltages for the various available options.
5.000
VDD, V2MON, V3MON Vth (V)
4.500
4.000
3.500
3.000
2.500
2.000
1.500
1.000
0.500
0.000
-40
Vth = 0.60V
25
TEMPERATURE (°C)
85
Vth = 3.09V
Vth = 4.64V
Adjusting t
POR
On the ISL88021 and ISL88022, users can adjust the Power-
On-Reset timeout delay (t
POR
) to many times the nominal
t
POR
. Figure 2 illustrates the effect of capacitance on the C
POR
pin to ground, showing changing t
POR
with a graph normalized
to 175ms for an open C
POR
pin. The maximum recommended
capacitance that should be placed on the C
POR
pin is 50pF.
NOTE:
Care should be taken in PCB layout and capacitor
placement in order to eliminate stray capacitance as much as
possible, which contributes to t
POR
error.
10
Normalized t
POR
8
6
4
2
0
1
5
9 13 17 21 25 29 33 37 41 45
C
POR
(pF)
FIGURE 2. NORMALIZED t
POR
vs C
POR
GRAPH
Vth = 2.92V
Vth = 2.32V
Vth = 1.69V
FIGURE 1. VDD, V2MON, V3MON VTH vs TEMP
FN8226 Rev 1.00
September 18, 2006
Page 4 of 8
ISL88021, ISL88022
Manual Reset
The manual reset input (MR) allows the user to trigger a reset by
using a push-button switch or by signaling that pin low. The MR
input is an active low debounced input. By connecting a push-
button directly from MR to ground, the designer adds manual
system reset capability. Reset is asserted if the MR pin is pulled
low to less than 100mV for 1µs or longer while the push-button is
closed or a reset is signaled. After MR is released, the reset
outputs remain asserted for t
POR
. MR input has an internal 20k
pull up resistor provided.
Figure 3 illustrates a typical application diagram for either IC
showing both reset outputs being used along with both a manual
and signalled reset configuration. The V
DD
and V2MON
thresholds are preset whereas the V3MON is capable of UV
(ISL88021) or OV (ISL88022) monitoring of a voltage greater than
or less than 0.6V, respectively.
TO DISPLAY
3.3V - 5V
V
DD
V2MON
1.8V - 3.3V
ISL88021
ISL88022
V3MON
V
MON
> 0.6V
GND
C
POR
RST
RST
MR
PB
TO µP
ISL88022IU8HFZ
RESET
SIGNAL
ISL88021IU8HFZ
FIGURE 3. TYPICAL APPLICATION DIAGRAM
Application Considerations
Follow good decoupling practices to prevent transients from
causing unwanted reset signaling due to switching noises and
short duration droops.
When using the C
POR
pin, reduce layout stray capacitance on
this pin to minimize effect on t
POR
timing. If no PCB C
POR
pad
is patterned, the t
POR
can be 160ms.
FIGURE 4. ISL88021_22EVAL1 SCHEMATIC AND PHOTO
MONITORED VOLTAGE RISING AND FALLING RAMP
THROUGH THE PROGRAMMED UV AND OV THRESHOLDS
Using the ISL88021_22EVAL1 Platform
The ISL88021_22EVAL1 board is designed to provide both
immediate functional assessment and flexibility to the user. Both
ICs are the ‘HF’ variant having a V
DD
Vth of 4.64V, a V2MON
Vth of 3.09V and V3MON Vth of 0.6V. The top IC position is the
ISL88021 and is configured to monitor for undervoltage (UV)
compliance of a 5V, 3.3V and a 2.5V and signaling the RESET
and RESET outputs. The bottom position is the ISL88022
variant, which is configured to measure a 3.3V overvoltage
(OV) in addition to UV on both the 5V and 3.3V supplies.
RESET and RESET is asserted for at least t
POR
when these
voltage go out of range. In both cases V3MON interfaces with
the monitored supply via a simple resistor divider for comparison
to the internal 0.6V reference. A Manual Reset (MR) input is
provided on both ICs and is invoked by pulling this input LOW.
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