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MMSF2P02E
Preferred Device
Power MOSFET
2 Amps, 20 Volts
P−Channel SO−8
These miniature surface mount MOSFETs feature ultra low R
DS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a low reverse recovery time. MiniMOSt
devices are designed for use in low voltage, high speed switching
applications where power efficiency is important. Typical applications
are dc−dc converters, and power management in portable and battery
powered products such as computers, printers, cellular and cordless
phones. They can also be used for low voltage motor controls in mass
storage products such as disk drives and tape drives. The avalanche
energy is specified to eliminate the guesswork in designs where
inductive loads are switched and offer additional safety margin against
unexpected voltage transients.
•
Ultra Low R
DS(on)
Provides Higher Efficiency and Extends Battery
Life
•
Logic Level Gate Drive
−
Can Be Driven by Logic ICs
•
Miniature SO−8 Surface Mount Package
−
Saves Board Space
•
Diode Is Characterized for Use In Bridge Circuits
•
Diode Exhibits High Speed
•
Avalanche Energy Specified
•
Mounting Information for SO−8 Package Provided
•
I
DSS
Specified at Elevated Temperature
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted) (Note 1.)
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
−
Continuous
Drain Current
−
Continuous @ T
A
= 25°C (Note 2.)
−
Continuous @ T
A
= 100°C
−
Single Pulse (t
p
≤
10
μs)
Total Power Dissipation @ T
A
= 25°C
(Note 2.)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy
−
Starting T
J
= 25°C
(V
DD
= 20 Vdc, V
GS
= 5.0 Vdc,
I
L
= 6.0 Apk, L = 12 mH, R
G
= 25
Ω)
Thermal Resistance
−
Junction to Ambient
(Note 2.)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Symbol
V
DSS
V
GS
I
D
I
D
Value
20
±
20
2.5
1.7
13
2.5
−
55 to
150
216
Unit
Vdc
Vdc
Adc
Apk
Watts
°C
mJ
8
1
L
Y
WW
= Location Code
= Year
= Work Week
http://onsemi.com
2 AMPERES
20 VOLTS
R
DS(on)
= 250 mW
P−Channel
D
G
S
MARKING
DIAGRAM
SO−8
CASE 751
STYLE 13
S4P01
LYWW
I
DM
P
D
T
J
, T
stg
E
AS
PIN ASSIGNMENT
N−C
Source
Source
Gate
1
2
3
4
8
7
6
5
Drain
Drain
Drain
Drain
Top View
R
θJA
T
L
50
260
°C/W
°C
ORDERING INFORMATION
Device
MMSF2P02ER2
Package
SO−8
Shipping
2500 Tape & Reel
1. Negative sign for P−Channel device omitted for clarity.
2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided),
10 sec. max.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 6
1
Publication Order Number:
MMSF2P02E/D
MMSF2P02E
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted) (Note 3.)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
μAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 20 Vdc, V
GS
= 0 Vdc)
(V
DS
= 20 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 4.)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
μAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 2.0 Adc)
(V
GS
= 4.5 Vdc, I
D
= 1.0 Adc)
Forward Transconductance (V
DS
= 3.0 Vdc, I
D
= 1.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 5.)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 16 Vdc, I
D
= 2.0 Adc,
V
GS
= 10 Vdc)
(V
DD
= 10 Vdc, I
D
= 2.0 Adc,
V
GS
= 10 Vdc,
R
G
= 6.0
Ω)
(V
DD
= 10 Vdc, I
D
= 2.0 Adc,
V
GS
= 5.0 Vdc,
R
G
= 6.0
Ω)
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 4.)
Reverse Recovery Time
(I
S
= 2.0 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/μs)
Reverse Recovery Stored Charge
3. Negative sign for P−Channel device omitted for clarity.
4. Pulse Test: Pulse Width
≤
300
μs,
Duty Cycle
≤
2%.
5. Switching characteristics are independent of operating junction temperature.
(I
S
= 2.0 Adc, V
GS
= 0 Vdc)
V
SD
t
rr
t
a
t
b
Q
RR
−
−
−
−
−
1.5
34
18
16
0.035
2.0
64
−
−
−
μC
Vdc
ns
−
−
−
−
−
−
−
−
−
−
−
−
20
40
53
41
13
29
30
28
10
1.1
3.3
2.5
40
80
106
82
26
58
60
56
15
−
−
−
nC
ns
ns
(V
DS
= 16 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
340
220
75
475
300
150
pF
V
GS(th)
Vdc
1.0
2.0
4.7
0.19
0.3
2.8
3.0
−
0.25
0.4
−
Mhos
mV/°C
Ohm
−
−
1.0
V
(BR)DSS
Vdc
20
−
−
−
−
−
24.7
−
−
−
−
−
1.0
10
100
mV/°C
μAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
R
DS(on)
g
FS
http://onsemi.com
2
MMSF2P02E
TYPICAL ELECTRICAL CHARACTERISTICS
4
V
GS
= 10 7 V
I D , DRAIN CURRENT (AMPS)
3
4.3 V
2
4.1 V
3.9 V
1
3.7 V
3.5 V
3.3 V
0
0.4
0.8
1.2
1.6
2
5V
4.7 V
4.5 V
T
J
= 25°C
I D , DRAIN CURRENT (AMPS)
3
100°C
2
25°C
T
J
= −55°C
1
4
V
DS
≥
10 V
0
0
2.5
3
3.5
4
4.5
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0.6
0.5
0.4
0.3
0.2
0.1
0
3
4
5
6
7
8
9
10
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
I
D
= 1 A
T
J
= 25°C
0.6
Figure 2. Transfer Characteristics
T
J
= 25°C
0.5
0.4
V
GS
= 4.5
0.3
0.2
10 V
0.1
0
0.5
1
I
D
, DRAIN CURRENT (AMPS)
1.5
2
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.0
V
GS
= 10 V
I
D
= 2 A
1.5
I DSS , LEAKAGE (nA)
100
V
GS
= 0 V
T
J
= 125°C
10
1.0
0.5
100°C
0
−50
−25
0
25
50
75
100
125
150
1
0
4
8
12
16
20
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
http://onsemi.com
3
Figure 6. Drain−to−Source Leakage Current
versus Voltage
MMSF2P02E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
V
DS
= 0 V
C
iss
V
GS
= 0 V
T
J
= 25°C
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1000
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
12
QT
9
V
DS
6
Q1
Q2
V
GS
16
800
C, CAPACITANCE (pF)
12
600
8
400
C
rss
C
iss
C
oss
C
rss
200
0
10
3
Q3
4
I
D
= 2 A
T
J
= 25°C
2
4
6
8
Q
g
, TOTAL GATE CHARGE (nC)
10
0
12
5
V
GS
0
V
DS
5
10
15
20
25
30
0
0
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
http://onsemi.com
4
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
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