SiT3907
High Precision Digitally Controlled Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
Factory programmable between 1 MHz and 220 MHz
Digitally controlled pull range: ±25, ±50, ±100, ±200, ±400, ±800,
±1600 PPM
Eliminate the need for an external DAC
Superior pull range linearity of <= 0.01%
LVCMOS/LVTTL compatible output
Three industry-standard packages: 3.2 mm x2.5 mm (4-pin), 5.0 mm
x 3.2 mm (6-pin), 7.0 mm x 5.0 mm (6-pin)
Programmable drive strength to reduce EMI
Outstanding silicon reliability of 2 FIT
Ideal for clock synchronization, instrumentation, low
bandwidth PLL, jitter cleaner, clock recovery, audio,
video, and FPGA
Electrical Characteristics
Parameters
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
F_aging
T_use
Min.
1
-10
-25
-50
Aging
Operating Temperature Range
-5
-20
-40
1.71
Supply Voltage
Vdd
2.25
2.52
2.97
Pull Range
Linearity
Frequency Change Polarity
Frequency Update Rate
Current Consumption
Duty Cycle
Rise/Fall Time
Output High Voltage
Output Low Voltage
Output Load
Start-up Time
Input Low Voltage
Input Middle Voltage
Input High Voltage
Input High or Low Logic Pulse
Input Middle Pulse Width
Input Impedance
Input Capacitance
RMS period Jitter
RMS Phase Jitter (random)
PR
Lin
–
F_update
Idd
DC
Tr, Tf
VOH
VOL
Ld
T_start
VIL
VIM
VIH
T_logic
T_middle
Zin
Cin
T_jitt
T_phj
–
–
–
–
45
–
90
–
–
–
–
0.4xVdd
0.8xVdd
500
500
100
–
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
1.8
2.5
2.8
3.3
±400, ±800, ±1600
–
Positive Slope
–
–
32
31
–
1.2
–
–
–
6
–
–
–
–
–
–
5
1.5
2
0.6
0.65
25
12.5
34
34
55
2
–
10
15
10
0.2xVdd
0.6xVdd
–
–
–
–
–
2
3
1
1
0.01
Max.
220
+10
+25
+50
+5
+70
+85
1.89
2.75
3.08
3.63
Unit
MHz
PPM
PPM
PPM
PPM
°C
°C
V
V
V
V
PPM
%
–
kU / s
kU / s
mA
mA
%
ns
%Vdd
%Vdd
pF
ms
V
V
V
ns
ns
kΩ
pF
ps
ps
ps
ps
20% to 80%
f = 20 MHz, all Vdds
f = 20 MHz, all Vdds
f = 20 MHz, Integration bandwidth = 12 kHz to 20 MHz,
all Vdds. No activity on DP pin.
With full activity on DP pin.
See Figure 5
See Figure 5
See Figure 5
See Figure 5
See Figure 5
Frequency control mode 1, see Table 1
Frequency control mode 2, see Table 2
No load condition, f = 100 MHz, Vdd = 2.5V, 2.8V or 3.3V
No load condition, f = 100 MHz, Vdd = 1.8 V
Vdd = 1.8V, 2.5V, 2.8V or 3.3V
Vdd =1.8V, 2.5V, 2.8V or 3.3V, 10% - 90% Vdd level
IOH = -6mA, Vdd = 3.3V, 2.8V, 2.5V
IOL = -3mA, Vdd = 1.8V
IOH = -6mA, Vdd = 3.3V, 2.8V, 2.5V
IOL = -3mA, Vdd = 1.8V
See the last page for Absolute Pull Range, APR table
10 years
Extended Commercial
Industrial
Inclusive of initial tolerance, operating temperature, rated
power, supply voltage and load change
Condition
±25, ±50, ±100, ±200
Notes:
1. Absolute Pull Range (APR) is defined as the guaranteed pull range over temperature and voltage.
2. APR = pull range (PR) - frequency stability (F_stab) - Aging (F_aging)
SiTime Corporation
Rev. 1.2
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised July 24, 2014
SiT3907
High Precision Digitally Controlled Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
Pin Description (4-pin device)
Pin
1
2
3
4
Map
Digital Programming Pin (DPpin)
GND
CLK
VDD
Electrical ground
[3]
Oscillator output
VDD power supply
[3]
Functionality
See “Frequency Control Protocol Description” section
Top View
DP
1
GND
2
4
VDD
CLK
3
Pin Description (6-pin device)
Pin
1
2
3
4
5
6
Map
Digital Programming Pin (DPpin)
NC
GND
CLK
NC
VDD
No connect
Electrical ground
[3]
Oscillator output
No connect
VDD power supply
[3]
Functionality
See “Frequency Control Protocol Description” section
Top View
DP
1
NC
2
GND
3
6
VDD
NC
CLK
5
4
Note:
3. A capacitor value of 0.1 µF between VDD and GND is required.
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual performance of the IC
is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
–
–
Max.
150
4
2000
260
Unit
°C
V
V
°C
Absolute Maximum
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.2
Page 2 of 10
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SiT3907
High Precision Digitally Controlled Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
Description
SiT3907 device is a digitally controlled programmable oscillator (DCXO), which allows pulling the frequency around a nominal
value dynamically. User can communicate with the device through a 1-pin tri-level serial interface. This device has two DCXO
registers, which control the amount of frequency pull. Once the registers are set, the device sets its output frequency to a new
value dynamically. The pull range is programmable to a maximum of ±1600 PPM. The resolution varies between1 part-per-billion
(ppb) and 50 ppb depending on total pull range selected. Writing into the DCXO registers does not cause any interruptions of
output oscillations; the frequency will switch from one value to the new one smoothly.
The device allows two modes of operation. In mode 1, user can set one of the DCXO registers to control frequency. In mode 2,
the user can set both registers to achieve better resolution while maintaining wide pull ranges.
Default Startup Condition
The SiT3907 starts up at its factory programmed frequency. The DCXO registers values are initialized all zeros,
effectively setting the frequency to the middle of the control range.
Frequency Control Protocol Description
The device includes two DCXO registers. Data for each register is written to the device using a data frame.
Data Frame Format
Each frame consists of 40 bits. A frame has 3 parts:
- The header, 16 bits
- Register address, 8 bits
- Pull frequency (PF) value represented as 2's complement binary number, 16 bits or 23 bits depending on programming mode
explained in the following paragraphs.
Most significant bits of a frame are sent first. When writing to both DCXO registers, the least significant word is sent first.
The header allows the devices to recognize that the master is initiating communication. The header includes the device
address, which is factory programmable. The valid header format is 0xFAIA, where "I" can be a hex digits from 0 to F. If not
specified at the order time, the device address will be defaulted to zero. For all examples and in this document, the device
address is considered to be zero (default).
0
15 16
23 24
39
Header
0xFA 0A
(1 6 b its )
Frequency Control Mode 1
R e g A d d re s s
0x06 or 0x07
(8 b its )
P u ll F re q u e n c y V a lu e
(1 6 b its )
Frequency Control Mode 2
In this mode, two frames per frequency update are required, and fre-
quency is only updated at the end of the second frame. The pull fre-
quency value in this mode is 23 bits. This value is written to the
device in two frames as Figure 2. Note that register (address: 0x07)
carries the most significant 7 bits as indicated by the XXXXXXX in
Figure 2. The rest of the most significant bits must be set to 0.
In this resolution mode, only one frame per frequency update is
required, and the output frequency is updated at the end of each
frame. The length of the pull frequency data is 16 bits, and is written
to the device as shown below:
First frame
Header
(16 bits) 0xFA0A
Register
address
(8 bits) 0x07
Pull frequency value
(LS Word, 16 bits)
000000000xxxxxxx
Header
(16 bits) 0xFA0A
Register
address
(8 bits) 0x06
Pull frequency value
(16 bits)
Second frame
Header
(16 bits) 0xFA0A
Register
address
(8 bits) 0x06
Pull frequency value
(MS word, 16 bits)
Figure 1. Frequency Control Mode 1
Figure 2. Frequency Control Mode 2
Rev. 1.2
Page 3 of 10
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SiT3907
High Precision Digitally Controlled Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
Max Update Rate
(Updates Per Second)
25 K
25 K
25 K
25 K
25 K
25 K
25 K
Max Update Rate
(Updates Per Second)
12.5 K
12.5 K
12.5 K
12.5 K
12.5 K
12.5 K
12.5 K
Pull Range (PPM)
±25
±50
±100
±200
±400
±800
±1600
Step Resolution (ppb)
1
1.5
3
6
12
25
49
Pull Range (PPM)
±25
±50
±100
±200
±400
±800
±1600
Step Resolution (ppb)
1
1
1
1
1
1
1
Table 1. Resolution and Update Rate for Mode 1
Table 2. Resolution and Update Rate for Mode 2
Control pin
0xFA0A
0x06
0xPF
1
0xFA0A
0x06
0xPF
2
T
f2f
f
0
+ PF
1
Output
frequency
f
0
T
frame
T
fdelay
T
settle
f
0
+ PF
2
Figure 3. Mode 1 Frame Timing
Control pin
0xFA0A
0x07
0xPF
1
(LSB)
0xFA0A
0x06
0xPF
1
(MSB)
f
0
+ PF
1
Output
frequency
f
0
T
frame
T
f2f
T
frame
T
fdelay
T
settle
Figure 4. Mode 2 Frame Timing
Frame Timing Parameters
Parameter
Frame Length
Frame to Frame Delay
Frequency Settling Time
Frame to Frequency Delay
Symbol
T
frame
T
f2f
T
settle
T
fdelay
Min.
40
2
—
—
Max.
—
—
30
8
Unit
S
S
S
S
Calculating Pull Frequency Values
The frequency control value must be encoded as a 2's complement number (16-bit in mode 1 and 23-bit in mode 2), represent-
ing the full scale range of the device. For example, for a ±1600ppm device in mode 2, the 23-bit number represents the full
±1600ppm range.
The upper 16 bits of the value are written to address 0x06. If the high-resolution register (address 0x07) is used, the other 7 bits
are written to the lowest seven bits of address 0x07.
Here are the steps to calculate the pull frequency (PF) value:
1. Find the scale factor (calculated for half of the pull range) from the tables below where PR is the Pull Range:
K (scale) Factor
Mode
K = Scale Factor
1
2
(2^15-1) / (PR*1.00135625)
(2^22-1) / (PR*1.00135625)
2. Enter the desired_PPM in equation below:
Frequency control (decimal value) = round (desired_PPM * K).
3. For any frequency shifts (positive or negative PPM), convert the frequency control value to a 2’s complement binary number.
Rev. 1.2
Page 4 of 10
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SiT3907
High Precision Digitally Controlled Oscillator (DCXO)
The Smart Timing Choice
The Smart Timing Choice
Two examples follow:
Example 1
This example shows how to shift the frequency by +245.6 ppm in a
device with ±1600 pull range using Mode 2 (23-bit):
Decimal value: round(245.6 * K) = 642954
23-bit value = 0x09CF8A
LS Word value = 0x000A (to be written to address 0x07)
MS Word value = 0x139F (to be written to address 0x06)
Write LS Word: 0xFA0A 07 000A (Frequency will not update)
Write MS Word: 0xFA0A 06 139F (Frequency updates after write)
Example 2
This example shows how to shift the frequency by -831.2 ppm in a
device with ±1600 pull range using Mode 2 (23-bit):
Decimal value: round(abs(831.2 * K) = 2175989
23-bit abs binary value: 01000010011001111110101
23-bit 2's comp binary value: 1011110110011000 0001011
LS Word value = 0x 000B
MS Word value = 0x BD98
Write LS Word: 0xFA0A 07 000B (Frequency will not update)
Write MS Word: 0xFA0A 06 BD98 (Frequency updates after write)
Physical Interface
The SiTime DCMO uses a serial input interface to adjust the pull frequency value. The interface uses a one-wire tri-level
return-to-middle signaling format. Figure 5 below shows the signal waveform of the interface.
T _ b it
“0 ”
0 .8 x V D D
0 .7 x V D D
0 .6 x V D D
0 .4 x V D D
0 .3 x V D D
0 .2 x V D D
T _ b it
“1 ”
V IH
V IM
V IL
T _ lo g ic
T _ lo g ic
T _ m id d le
Figure 5. Serial 1-Wire Tri-Level Signaling
A logical bit “1” is defined by a high-logic followed by mid-logic. A logical bit “0” is defined by a low-logic followed by mid-logic.
The voltage ranges and time durations corresponding to low-logic, high-, and mid-logic are illustrated in Figure 5 and specified
in electrical specification table.
The overall baud rate is computed as below:
baud
_
rate
½
1
T
_
bit
Figure 6 shows a simple circuit to generate tri-level circuit with a general purpose IO (GPIO) with tri-state capability. Most
FPGAs and micro controllers/processors include such GPIOs. If the GPIO does not support tri-state output, two IO s may be
used in combination with external tri-state buffer to generate the tri-level signal; an example of such buffer is the
SN74LVC1G126. The waveform at the output of the tri-state buffer is shown in Figure 7. When the GPIO drives Low or High
voltage, the rise/fall times are typically fast (sub-5ns range). When the output is set to Hi-Z, the output settles at middle voltage
with a RC response. The time constant is determined based on the total capacitance on frequency control pin and the parallel
resistance of the pull-up and pull-down resistors. The time constant in most practical situations will be less than 50ns; this
necessitate choosing longer T_middle to allow the RC waveform to settle within 5% or so.
Rev. 1.2
Page 5 of 10
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