DEMO MANUAL DC1931B
LTM9013
300MHz Wideband/DPD Receiver
Description
Demonstration circuit DC1931 is a 300MHz wideband/
digital pre-distortion (DPD) receiver subsystem featuring
the
LTM
®
9013.
The DC1931 card is designed to plug into
the DC1371 data acquisition demo board. It is configured
with an IF highpass filter, designed to provide a corner
frequency of approximately 1MHz. Other corner frequencies
may be realized by changing a small number of element
values on the DC1931; see the LTM9013 data sheet for
details. The digital output can easily be analyzed with
Linear Technology’s PScope™ data processing software,
which is available for no charge at
http://www.linear.com.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
Quick start proceDure
Validating the performance of the LTM9013 is simple
with DC1931, and requires only two input sources, a
clock source, a computer, and a lab power supply. The
DC1931 demonstration circuit board should have the
jumper settings as default positions (as per Table 1)
which configures the ADC in serial programming mode.
In the default configurations, JP1-JP4 should be left in the
default locations. This will pull the SPI lines high through
weak pull-up resistors so that the SPI commands can be
sent from the PC. When JP1 is set to PAR, then jumpers
JP2-JP4 can be configured manually. Refer to Figure 1
for proper board evaluation equipment setup and follow
the procedure below:
1. Connect the power supply as shown in Figure 1. There
are onboard low noise voltage regulators that provide
the three supply voltages for the LTM9013. The entire
board and all components share a common ground.
The power supply should still be a low noise lab power
supply capable of supplying at least 1A.
2. Provide an encode clock to the ADC via SMA connector
J3. Use a low phase-noise clock source such as a filtered
RF signal generator or a high quality clock oscillator.
Note:
Similar to having a noisy input, a high jitter (phase
noise) encode clock will degrade the signal-to-noise ratio
(SNR) of the system.
3. Apply an RF input signal via SMA connector J1. For
best results, use a low distortion, low noise signal
Table 1: DC1931 Connectors and Jumpers
REFERENCE
J1 (RF)
J2 (LO)
J3 (CLK)
FUNCTION
Board RF Signal Input. Impedance-Matched to 50Ω
for Use with Lab Signal Generators.
Board LO Signal Input. Impedance-Matched to
50Ω for Use with Lab Signal Generators.
Board Clock Input. Impedance-Matched to 50Ω.
Drive with a Low Phase Noise Clock Oscillator or
Filtered Sine Wave Signal Source.
DC1371 Interface Connector.
Selects Serial or Parallel Configuration Setting.
Default is SER. (Refer to Data Sheet for Function of
JP2-JP4 in Serial Mode.)
J4 (digital data)
JP1(I/0)
JP2 (CLK Stabilizer) Enables Clock Duty Cycle Stabilizer.
Default is Disable.
JP3 (ADC Sleep)
JP5 (Amp Run)
JP6 (I/Q Enable)
JP7 (IP2 Adjust)
JP8 (Write Enable)
Sets ADC Sleep mode. Default is RUN.
Enables IF Amplifier. Default is EN.
Enables I/Q Demodulator. Default is EN.
Enables IP2 Adjust. Default is Disable.
Enables/Disables Writing to the EEPROM.
Default is EN.
JP4 (LVDS Current) Selects LVDS Output Current. Default is 3.5mA
generator with sufficient filtering to avoid degrading
the performance of the receiver.
4. Apply an LO input signal via SMA connector J2. Note
that the difference in frequency between this signal and
the RF signal will be the baseband frequency resulting
at the I and Q channels and ADC inputs.
dc1931bfa
1
DEMO MANUAL DC1931B
Quick start proceDure
5. Observe the ADC output with demo circuit DC1371, a
USB cable, a Windows computer, and Linear Technol-
ogy’s PScope data processing software.
6. Note the IF gain of the LTM9013 may be adjusted using
R25 (I channel), and R31 (Q channel).
7. The 2nd order linearity of the LTM9013 may be ad-
justed over a limited range by first setting JP7 to the
EN position, and then using R15 (I channel) and R7
(Q channel).
Using PScope Software
PScope, downloadable from Linear Technology’s website
http://www.linear.com/software, processes data from the
DC1371 data acquisition board and displays FFT and signal
analysis information on the computer screen.
The onboard EEPROM U5 should enable automatic board
detection and auto-configuration of the software, but if the
user wishes to change the settings, they can easily do so.
Figure 2. Entering the Correct Device Information for Your
ADC. Select the Correct Parameters for the DC1931. Under
Normal Conditions, PScope Should Automatically Recognize
the Board and Adjust the Software Settings Accordingly
From the Configure menu in the toolbar, uncheck
“Autodetect Device”. The default settings for DC1931 are
shown in Figure 2.
SIGNAL
GENERATOR
SMB100 OR EQUIV.
Note:
Even a high quality signal synthesizer will still have noise
and harmonics that should be attenuated with a lowpass or
bandpass filter. For good quaility high order filters, see TTE,
Lark Engineering, or equivalent.
BPF
SIGNAL
GENERATOR
SMB100 OR EQUIV.
BPF
TO DC1371
RF SIGNAL GENERATOR
(HP 8644B) OR OTHER
LOW PHASE NOISE
CLOCK SOURCE
(e.g., DC1216)
BPF
POWER SUPPLY
(5V AT 1000mA)
Figure 1. Proper Measurement Equipment Setup
2
dc1931bfa
DEMO MANUAL DC1931B
parts List
ITEM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
QTY
9
3
1
0
0
2
2
7
2
1
2
1
1
8
8
3
4
1
1
4
2
1
4
4
1
2
2
4
4
2
2
12
1
1
1
6
2
2
2
1
1
1
1
REFERENCE
C12-C15, C33, C34, C36-C38
C29, C32, C35
C19
C21, C27, R36, R38
C2, C3, C8, C9
C17, C18
C31, C30
C1, C6, C7, C16, C23, C25, C26
C5, C11
C20
C4, C10
C24
J4
JP1-JP8
JP1-JP8
J1, J2, J3
R11, R20, R35, R39
C22
L5
L1, L2, L3, L4
R6, R12
R29
R5, R8, R14, R22
R16, R17, R18, R19
R43
R33, R28
R26, R37
R9, R44, R45, R46
R7, R15, R25, R31
R23, R30
R42, R40
R1, R2, R3, R4, R10, R13, R21, R24,
R27, R32, R34, R47
R41
T2
T1
E1, E2, E3, E4, E5, E6
E7, E8
U7, U1
U4, U3
U5
U2
PART DESCRIPTION
CAP, X5R, 0.1µF, 10V, 10%, 0402
CAP, TANT, 47µF, 10V, 10%, C 6032
CAP, C0G, 100pF, 25V, 1%, 0402
CAP, DNI, 0402
CAP, DNI, 0805
CAP, X7R, 2.2µF, 6.3V, 10%, 0603
CAP, X5R, 4.7µF, 10V, 20%, 0805
CAP, X7R, 0.01µF, 16V, 10%, 0402
CAP, X7R, 0.01µF, 16V, 10%, 0805
CAP, C0G, 1.5pF, 25V, 1%, 0402
CAP, C0G, 6.8pF, 25V, 1%, 0402
CAP, C0G, 0.5pF, 25V, 1%, 0402
CONN., SNGL-END ARRAY MALE 160POS
HEADER, 3X1, 2mm
SHUNT
CONN, SMA, 50Ω EDGE-LAUNCH
RES, 0Ω JUMPER, 0402
IND, 6.8nH, 5%, 0402
IND, 3.3nH, 5%, 0402
IND, 15nH, 5%, 0402
RES, 3.83k, 1%, 1/16, 0402
RES, 1.58k, 1%, 1/16, 0402
RES, 100Ω, 1%, 1/16, 0603
RES, 0.1Ω, 1%, 1/10, 0603
RES, 182k, 1%, 1/10, 0603
RES, 178Ω, 1%, 1/16, 0402
RES, 49.9Ω, 1%, 1/20, 0201
RES, 10k, 1%, 1/16, 0402
POT., TRIMMER, 1kΩ 1/4” SQ CERM SL ST
RES, 1.74k, 1%, 1/16, 0402
RES, 3.00k, 1%, 1/16, 0402
RES, 1k, 5%, 1/16, 0402
RES, 330K OHM, 1%, 1/10, 0603
TRANSFORMER, RF, SMT, 1:1 BALUN
TRANSFORMER, RF, SMT, 4:1 BALUN
TURRET, 0.063
TURRET, 0.094
IC, CMOS FET, SI1563DH
IC, VREG,ADJ,1.1A,DD8
IC EEPROM 32KBIT 400KHZ 8TSSOP
MODULE, LTM9013IY
FAB, PCB, DC1931B
STENCIL SET, DC1931B
MANUFACTURER/PART NUMBER
AVX, 0402ZD104KAT2A
VISHAY/293D476X9010C2TE3
AVX, 04023A101FAT
AVX, 06036C225KAT2A
AVX, 0805ZD475MAT2A
AVX, 0402YC103KAT2A
AVX, 0805YC103KAT2A
AVX, 04023A1R5FAT
AVX, 04023A6R8FAT
AVX, 04023A0R5FAT
SAMTEC, ASP-134606-01
SULLIN, NRPN031PAEN-RC
SAMTEC, 2SN-BK-G
E.F.JOHNSON, 142-0701-851
VISHAY, CRCW04020000Z0ED
TOKO, LL1005-FHL6N8J
TOKO, LL1005-FHL3N3J
TOKO, LL1005-FHL15NJ
VISHAY, CRCW04023K83FKED
VISHAY, CRCW04021K58FKED
VISHAY, CRCW0603100RFKED
VISHAY, WSL0603R1000FEA
VISHAY, CRCW0603182KFKEA
VISHAY, CRCW0402178RFKED
VISHAY, CRCW020149R9FKED
VISHAY, CRCW040210K0FKED
BOURNS, 3362P-1-102TLF
VISHAY, CRCW04021K74FKED
VISHAY, CRCW04023K00FKED
VISHAY, CRCW04021K00JNED
VISHAY, CRCW0603330KFKEA
MA COM, MABA-007159-000000
ANAREN, BD0826J50200A00
MILL-MAX, 2308-02-00-80-00-00-07-0
MILL-MAX, 2501-02-00-80-00-00-07-1
VISHAY SILICONIX, SI1563DH
LINEAR TECH, LT3080EDD#PBF
MICROCHIP, 24LC32A-I/ST
LINEAR TECH, LTM9013IY
DEMO CIRCUIT DC1931B
STENCIL DC1931B
dc1931bfa
3
6
4
3
3
3
R6
3.83K
E1
2
5
1
3
1
1
1
R8
100
L2
15nH
C6
0.01uF
C7
0.01uF
R16
0.1
E2
E3
E4
R18
0.1
VCC1
VCC2
VDD
~CS
SCK
SDI
SDO
1
R9
10K
VCC1
VCC2
R10
1K
L3
15nH
C5
0.01uF
2
U1
Si1563DH
C2
DNI
C3
DNI
C4
6.8pF
JP1
R7
PARALLEL
SERIAL
2
JP2
CLOCK DUTY STABILIZE ON
CLOCK DUTY STABILIZE OFF
2
JP3
SLEEP
RUN
2
JP4
3
3
1
schematic Diagram
3
F4
F5
F10
F11
C6
C9
D9
E11
E10
E5
E4
J10
K10
J11
K11
L11
B7
D1
A2
A3
A12
D12
A13
J6
J9
1
-IN_I
+IN_I
-IN_Q
VCC1
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VDD
VDD
C17
3
R31
1.00K
2
B8
EN
EIP2
IP2_I
IP2_Q
GAIN_I
GAIN_Q
D6
C10
D10
R33
178
C12
C1
VDD
2.2uF
R29
1.58K
R30
1.74K
49.9
R28
178
JP7
C14
C3
D14
D3
EN#_I
EN#_Q
SHDN#_I
SHDN#_Q
PAR_SER#
CS#
SCK
SDI
SDO
R27
1K
+OUT_Q
-OUT_Q
+OUT_I
-OUT_I
+IN_Q
OVDD
OVDD
R26
VCC2
NC
NC
NC
GAIN ADJUST (I CH)
I/Q DISABLE
VCC1
N5
N10
DEMO MANUAL DC1931B
DEMOD REF
1
B4
C4
D4
G4
H4
J4
K4
L4
B5
C5
D5
G5
H5
L5
M5
B6
E6
F6
G6
H6
K6
L6
M6
N6
P6
A7
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
N7
A8
C8
E8
F8
G8
H8
K8
L8
M8
N8
A9
B9
E9
F9
G9
H9
K9
L9
M9
N9
P9
B10
G10
H10
L10
M10
A11
B11
C11
D11
G11
H11
B12
E12
F12
G12
H12
J12
K12
L12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
4
L1
15nH
C1
0.01uF
R2
1K
R4
1K
VDD
VDD
VDD
VDD
VCC2
VCC2
VCC1_load
R5
100
R1
1K
R3
1K
VCC1
VCC1
1.75 mA
3.5 mA
1.00K
AMP_MUTE (HI)
IP2 ADJUST (I CH)
R11
0
R12
3.83K
R15
1.00K
R13
1K
AMP RUN
2
~AMP_SHDN
C8
DNI
C9
DNI
VCC1_load
C10
6.8pF
C11
0.01uF
VCC1
VCC1_load
R17
0.1
JP5
R19
0.1
R14
100
B
IP2 ADJUST (Q CH)
AMP SHUTDOWN
VCC2
R20
0
R23
1.74K
L4
15nH
C16
C12
0.1uF
0.1uF
C13
0.01uF
R25
1.00K
R21
1K
R22
100
E5
VDD
C14
0.1uF
C15
0.1uF
VDD
I/Q ENABLE
2
U2
LTM9013
JP6
R24
1K
IP2 ADJUST ENABLE
IP2 ADJUST DISABLE
CLKOUT+
CLKOUT-
P8
P7
CLKOUT+
CLKOUT-
R32
1K
E6
GAIN ADJUST (Q CH)
C18
2.2uF
J8
SENSE
REF
D8
R34
1K
DA01+
DA01-
DA23+
DA23-
DA45+
DA45-
DA67+
DA67-
DA89+
DA89-
DA1011+
DA1011-
DA1213+
DA1213-
OF+
OF-
P12
P13
P10
P11
N12
N11
N14
N13
M12
M11
M14
M13
L14
L13
K2
K1
DA01+
DA01-
DA23+
DA23-
DA45+
DA45-
DA67+
DA67-
DA89+
DA89-
DA1011+
DA1011-
DA1213+
DA1213-
OF+
OF-
C19
A10
RF
C21
DNI
Matched for 1.95GHz
RF_IN
L5
3.3nH
J1
100pF
C20
1.5pF
Matched for 1.8GHz
1
LO-
LO+
4
A5
A6
6
C23
0.01uF
J5
K5
CLK+
CLK-
2
LO_IN
C22
6.8nH
T1
DB01+
DB01-
DB23+
DB23-
DB45+
DB45-
DB67+
DB67-
DB89+
DB89-
DB1011+
DB1011-
DB1213+
DB1213-
L2
L1
M2
M1
M4
M3
N2
N1
N4
N3
P4
P5
P2
P3
DB01+
DB01-
DB23+
DB23-
DB45+
DB45-
DB67+
DB67-
DB89+
DB89-
DB1011+
DB1011-
DB1213+
DB1213-
J2
C24
0.5pF
5
3
BD0826J50200A00
A
R35
T2
1
R37
49.9
3
R38
DNI
R39
0
C27
DNI
R36
DNI
0
C25
CLK_IN
5
J3
0.01uF
C26
4
0.01uF
MABA007159
A1
B1
E1
F1
G1
H1
J1
P1
B2
C2
D2
E2
F2
G2
H2
J2
B3
E3
F3
G3
H3
J3
K3
L3
A4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P14
K14
J14
H14
G14
F14
E14
B14
A14
K13
J13
H13
G13
F13
E13
D13
C13
B13
Title
Size
C
Date:
2
1
LTM9013 Demo Board
Document Number
DC1931
Friday, August 23, 2013
Sheet
1
of
2
Rev
B
dc1931bfa
U3
VCC2
VCC2
C33
+
DA1213+
DA1213-
DA89+
DA89-
DA45+
DA45-
DA01+
DA01-
DB1213+
DB1213-
DB89+
DB89-
DB45+
DB45-
DB01+
DB01-
OF+
OF-
0.1uF
C32
47uF
3
2
1
9
R40
3K
LT3080EDD
+3.3V
J4C
J4D
J4G
J4H
E7
+5V_IN
7
VIN
VOUT
+5V IN
+
PAD
C29
47uF
C30
C31
8
VIN
VOUT
4.7uF
4.7uF
VOUT
5
SET
VCTRL
DA1011+
DA1011-
DA67+
DA67-
DA23+
DA23-
4
schematic Diagram
E8
R48
10K
SDO
CLKOUT+
CLKOUT-
~CS
GND
C34
0.1uF
R41
330K
R50
10K
SCK
SCL
SDA
SDI
R49
10K
DB1011+
DB1011-
DB67+
DB67-
DB23+
DB23-
U4
VDD
VDD
C36
+
0.1uF
3
2
1
9
C35
47uF
R42
3K
LT3080EDD
+1.8V
7
VIN
VOUT
8
VIN
VOUT
VOUT
PAD
SEAM-10X40PIN
SEAM-10X40PIN
5
SET
VCTRL
GND
DP0_C2M_P
DP0_C2M_N
GND
GND
DP0_M2C_P
DP0_M2C_N
GND
GND
LA06_P
LA06_N
GND
GND
LA10_P
LA10_N
GND
GND
LA14_P
LA14_N
GND
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
GND
SCL
SDA
GND
GND
GA0
12P0V
GND
12P0V
GND
3P3V
GND
PG_C2M
GND
GND
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
GND
LA01_P_CC
LA01_N_CC
GND
LA05_P
LA05_N
GND
LA09_P
LA09_N
GND
LA13_P
LA13_N
GND
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LA26_P
LA26_N
GND
TCK
TDI
TDO
3P3VAUX
TMS
TRST_N
GA1
3P3V
GND
3P3V
GND
3P3V
SEAM-10X40PIN
SEAM-10X40PIN
GND
CLK0_C2M_P
CLK0_C2M_N
GND
GND
LA00_P_CC
LA00_N_CC
GND
LA03_P
LA03_N
GND
LA08_P
LA08_N
GND
LA12_P
LA12_N
GND
LA16_P
LA16_N
GND
LA20_P
LA20_N
GND
LA22_P
LA22_N
GND
LA25_P
LA25_N
GND
LA29_P
LA29_N
GND
LA31_P
LA31_N
GND
LA33_P
LA33_N
GND
VADJ
GND
VREF_A_M2C
PRSNT_M2C_N
GND
CLK0_M2C_P
CLK0_M2C_N
GND
LA02_P
LA02_N
GND
LA04_P
LA04_N
GND
LA07_P
LA07_N
GND
LA11_P
LA11_N
GND
LA15_P
LA15_N
GND
LA19_P
LA19_N
GND
LA21_P
LA21_N
GND
LA24_P
LA24_N
GND
LA28_P
LA28_N
GND
LA30_P
LA30_N
GND
LA32_P
LA32_N
GND
VADJ
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
C37
0.1uF
4
R43
182K
R44
10K
R45
10K
8
U5
24LC32A-I /ST
VCC
R47
1K
SCL
R46
10K
C38
0.1uF
U6
GND
FMC_MOUNTING_HOLE
U8
SDA
6
4
U7
Si1563DH
~AMP_SHDN
3
VCC1
VCC1
+5V
EN
EEPROM WRITE
2
JP8
1
3
4
VSS
2
5
SCL
SDA
WP
A2
A1
A0
FMC_MOUNTING_HOLE U9
FMC_MOUNTING_HOLE U10
1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
FMC_MOUNTING_HOLE
GND
DIS
GND
GND
6
5
7
3
2
1
Title
Size
C
Date:
LTM9013 Demo Board
Document Number
DC1931
Wednesday, February 06, 2013
Sheet
2
of
2
Rev
B
DEMO MANUAL DC1931B
dc1931bfa
5