DATASHEET
ISL55211
Wideband, Low Noise, Low Distortion, Fixed Gain, Differential Amplifier
The ISL55211 is a wideband, differential input to differential
output amplifier offering 3 possible internal gain settings.
Using fixed 500Ω internal feedback resistors, the amplifier
may be configured for a differential gain of 2, 4 or 5V/V
depending on which combination of input pins are connected
to the signal source. Internal feedback capacitors controls the
signal bandwidth to be a constant 1.4GHz in all gain settings.
Ideally suited for AC-coupled data acquisition applications, the
output DC common mode voltage is controlled through an
external V
CM
pin or left to default to 1.2V above the negative
supply pin. Where the differential signal source is AC-coupled,
the input common mode voltage will equal the output
common mode voltage.
Intended for very high dynamic range ADC interface
applications, the ISL55211 offers 5600V/µs differential slew
rate, <12nV/√Hz output noise, and >100dBc SFDR to
>100MHz for 2V
P-P
2-tone 3rd order intermodulation. Its
balanced architecture effectively suppresses even order
distortion terms - an important issue for very wide band 1st
Nyquist zone ADC interface applications. Minimum gain
operation of 2V/V (6dB) with <1dB peaking ensures stable
performance over-temperature. It's ultra high differential slew
rate of 5600V/µs provides adequate performance margin for
large signal application through 500MHz.
The ISL55211 requires only a single 3.3V (max. 4.2V) power
supply and 35mA quiescent current, providing a very low
power solution (115mW). Further power savings are possible
using the optional power shutdown control - where the
quiescent current can be reduced to <0.4mA. A companion
device, the ISL55210, offers similar performance where the
feedback and gain resistors are external. Both are available in
a 16 Ld TQFN (Pb-free) package and are specified for
operation over the -40°C to +85°C ambient temperature
range.
FN7868
Rev 0.00
June 21, 2011
Features
• 3 Fixed Gain Options . . . . . . . . . . . . . . . . . . . . . . . 2, 4, or 5V/V
• Constant Bandwidth Over Gain . . . . . . . . . . . . . . . . . . 1.4GHz
• Differential Slew Rate . . . . . . . . . . . . . . . . . . . . . . . 5,600V/µs
• 2V
P-P
, 2-tone IM3 (200Ω) 100MHz . . . . . . . . . . . . . . -103dBc
• Low Differential Output Noise (Gain 5V/V) . . . . . . <12nV/√Hz
• Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 3.0V to 4.2V
• Quiescent Power (3.3V Supply) . . . . . . . . . . . . . . . . . .115mW
Applications
• Low Power, High Dynamic Range ADC Interface
• Differential Mixer Output Amplifier
• SAW Filter Pre/Post Driver
• Fixed Gain Coax Receiver
Related Devices
•
ISL55210
- External Gain Set Version
•
ISLA112P50
- 12-bit, 500MSPS ADC (<500mW)
•
ISLA214P50
- 14-bit, 500MSPS ADC (<850mW)
Related Literature
•
AN1649
- “Designer’s guide to the ISL55210 and ISL55211
Evaluation Boards”
+3.3V
35mA
(115mW)
ISLA214P50
(850mW)
10
ADT2-1T 50
120nH
1:1.4
22pF
V
ADC
300
8pF
14Bit 500MSPS
ISL55211
50
ADT4-1T
V
CM
1.2V
G = 5V/V
180mV
P-P
For ADC -1dBFS
-
120nH
10
50
V
CM
20 log
V
ADC
= 20dB
V
i
GAIN (dB)
V
i
+
1:2
23
20
17
14
11
8
5
2
-1
-4
-7
-10
-13
1M
MEASURED FREQUENCY RESPONSE
10M
100M
1G
HIGH GAIN, VERY LOWPOWER, ADC INTERFACE WITH 3
RD
ORDER OUTPUT FILTER
FREQUENCY (Hz)
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FN7868 Rev 0.00
June 21, 2011
Page 1 of 20
ISL55211
Pin Configuration
ISL55211
(3x3 16 LD TQFN)
TOP VIEW
GND
16
V
S+
15
V
CM
14
GND
13
V
IN2-
1
348
750
500
0.2pF
12
V
O+
V
IN1-
2
140
140
750
-
V
CM
11
NC
V
IN1+
3
+
0.2pF
10
NC
V
IN2+
4
348
500
9
V
O-
5
6
7
8
GND
V
S+
GND
Pin Descriptions
PIN NUMBER
1
2
3
4
5, 8, 13, 16
6, 15
7
9
10, 11
12
14
SYMBOL
V
IN2-
V
IN1-
V
IN1+
V
IN2+
GND
V
S+
Pd
V
O-
NC
V
O+
V
CM
Pd
GND
DESCRIPTION
Balanced Differential Input for Av = 6dB, strapped to V
IN1-
for Av = 14dB
Balanced Differential Input for Av = 12dB, strapped to V
IN2-
for Av = 14dB
Balanced Differential Input for Av = 12dB, strapped to V
IN2+
for Av = 14dB
Balanced Differential Input for Av = 6dB, strapped to V
IN1+
for Av = 14dB
Supply Ground (thermal pad electrically connected)
Positive Power Supply (3.0V~4.2V)
Power-down: Pd = logic low. Puts part into low power mode; Pd = logic high or open for normal operation
Inverting Amplifier Output
No Internal Connection
Non-Inverting Amplifier Output
Common-mode Voltage Input
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL55211IRTZ
ISL55211IRTZ-EVAL1Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL55211.
For more information on MSL please see techbrief
TB363.
PART MARKING
5211
Evaluation Board
TEMP RANGE
(°C)
-40 to +85
PACKAGE
(Pb-free)
16 Ld 3x3 TQFN
PKG.
DWG. #
L16.3x3D
FN7868 Rev 0.00
June 21, 2011
Page 2 of 20
ISL55211
Absolute Maximum Ratings
(T
A
= +25°C)
Supply Voltage from V
S+
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
S+
+0.3V to GND-0.3V
Power Dissipation. . . . . . . . . . . . . . . . . . . . See Thermal Conditions Section
ESD Rating
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . 3500V
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . . . . . . . 250V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V
Latch up (Per JESD-78; Class II; Level A) . . . . . . . . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
16 Ld TQFN Package (Notes 4, 5) . . . . . . .
63
16.5
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
Max. Continuous Operating Junction Temperature . . . . . . . . . . . . .+135°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
V
S+
= +3.3V Test Conditions: G = 12dB, V
CM
= open, V
O
= 2V
P-P
, R
L
= 200 differential, T
A
= +25°C,
differential input, differential output, input and output referenced to internal default V
CM
(1.2V nominal) unless otherwise specified.
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
TESTED
Electrical Specifications
AC PERFORMANCE
Small-Signal Bandwidth (4-port S
parameter, Test Circuit 2)
G = 6dB, V
O
= 100mV
P-P
G = 12dB, V
O
= 100mV
P-P
G = 14dB, V
O
= 100mV
P-P
Bandwidth for 0.1-dB Flatness
Large-Signal Bandwidth
Gain Accuracy
G = 12dB, V
O
= 2V
P-P
(Figure 17)
G = 12dB, V
O
= 2V
P-P
G = 6dB, R
L
= Open
G = 12dB, R
L
= Open
G = 14dB, R
L
= Open
Slew Rate (Differential)
Differential Rise/Fall Time
2nd-order Harmonic Distortion,
Test Circuit 1, 15dB Gain
2-V step (simulated)
f = 20MHz, V
O
= 2V
P-P
f = 50MHz, V
O
= 2V
P-P
f = 100MHz, V
O
= 2V
P-P
3rd-order Harmonic Distortion,
Test Circuit 1, 15dB Gain
f = 20MHz, V
O
= 2V
P-P
f = 50MHz, V
O
= 2V
P-P
f = 100MHz, V
O
= 2V
P-P
2nd-order Intermodulation Distortion,
Test Circuit 1, 15dB Gain
3rd-order Intermodulation Distortion,
Test Circuit 1, 15dB Gain
Output Voltage Noise
f
c
= 70MHz, 200kHz spacing (2V
P-P
envelope)
f
c
= 140MHz, 200kHz spacing (2V
P-P
envelope)
f
c
= 70MHz, 200kHz spacing (2V
P-P
envelope)
f
c
= 140MHz, 200kHz spacing (2V
P-P
envelope)
Test Circuit 1, total gain 15dB, ADT2-1T
1.96
3.88
4.8
1.6
1.4
1.4
150
1.2
2
4
5
5,600
0.22
-110
-98
-85
-120
-110
-100
-89
-78
-104
-92
11.2
2.04
4.12
5.2
GHz
GHz
GHz
MHz
GHz
V/V
V/V
V/V
V/µs
ns
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
*
*
DC PERFORMANCE (Internal Nodes)
Input Offset Voltage
T
A
= +25°C
T
A
= -40°C to +85°C
-1.4
-1.6
±0.1
±0.1
+1.4
+1.6
mV
mV
*
FN7868 Rev 0.00
June 21, 2011
Page 3 of 20
ISL55211
V
S+
= +3.3V Test Conditions: G = 12dB, V
CM
= open, V
O
= 2V
P-P
, R
L
= 200 differential, T
A
= +25°C,
differential input, differential output, input and output referenced to internal default V
CM
(1.2V nominal) unless otherwise specified. (Continued)
PARAMETER
Average Offset Voltage Drift
Input Bias Current
CONDITIONS
T
A
= -40°C to +85°C
T
A
= +25°C, positive current into the pin
T
A
= -40°C to +85°C
Average Bias Current Drift
Input Offset Current
T
A
= -40°C to +85°C
T
A
= +25°C
T
A
= -40°C to +85°C
Average Offset Current Drift
T
A
= -40°C to +85°C
-5
-6
±8
MIN
(Note 6)
TYP
±3
+50
+50
200
±1
+5
+6
+120
+140
MAX
(Note 6)
UNIT
µV/
°
C
µA
µA
nA/
°
C
µA
µA
nA/
°
C
*
*
TESTED
Electrical Specifications
INPUT
Common-mode Input Range High
Common-mode Input Range Low
Common-mode Rejection Ratio
Differential Input Impedance
Internal Nodes
Internal Nodes
f < 10MHz, common mode to differential
output
V
IN1-
Connected to V
IN2-
V
IN1+
Connected to V
IN2+
1.1
56
75
200
1.7
V
V
dB
*
*
*
OUTPUT (Pins 9 AND 12)
Maximum Output Voltage
Minimum Output Voltage
Differential Output Voltage Swing
Each output (with 200differential load)
Linear Operation
T
A
= +25°C
T
A
= -40°C to +85°C
Differential Output Current Drive
Closed-loop Output Impedance
R
L
= 10[sourcing or sinking]
f < 10MHz, differential
2.15
2.35
0.45
3.04
2.95
40
45
0.6
3.8
0.63
V
V
V
P-P
V
mA
*
*
*
*
OUTPUT COMMON-MODE VOLTAGE CONTROL (Pin 14)
Small-signal Bandwidth
Slew Rate
Gain
Output Common-Mode Offset from CM Input
CM Default Voltage
CM Input Bias Current
CM Input Voltage Range
CM Input Impedance
Output V
CM
with V
CM
pin floating
At control pin
At control pin
At control pin
0.9
1550
From V
CM
pin to Output V
CM
Rising/Falling
V
CM
input pin 1.0V to 1.4V
0.995
-8
1.18
30
150
0.999
±1
1.2
2
1.9
+8
1.22
MHz
V/µs
V/V
mV
V
µA
V
kpF
*
*
*
*
POWER SUPPLY
Specified Operation Voltage
Quiescent Current
T
A
= +25°, V
S+
= 3.3V, V
S-
= 0V
T
A
= -40°C to +85°C
Power-supply Rejection (PSRR) V
S+
3.0V to 4.5V range
f < 10MHz [PSRR to differential output]
Referenced to GND
Assured on above 1.55V
Assured off below 0.54V
0.54
1.3
0.7
1.55
V
V
*
*
3
33
30.5
50
3.3
35
35
67
4.2
37
39.5
V
mA
mA
dB
*
*
*
POWER-DOWN (Pin 7)
Enable Voltage Threshold
Disable Voltage Threshold
FN7868 Rev 0.00
June 21, 2011
Page 4 of 20
ISL55211
V
S+
= +3.3V Test Conditions: G = 12dB, V
CM
= open, V
O
= 2V
P-P
, R
L
= 200 differential, T
A
= +25°C,
differential input, differential output, input and output referenced to internal default V
CM
(1.2V nominal) unless otherwise specified. (Continued)
PARAMETER
Power-down Quiescent Current
T
A
= +25°C
T
A
= -40°C to +85°C
Input Bias Current
Input Impedance
Turn-on Time Delay
Turn-off Time Delay
Measured to output on
Measured to output off
PD = 0V, current positive into pin
CONDITIONS
MIN
(Note 6)
0.2
0.15
-5
1
25
200
400
TYP
0.3
MAX
(Note 6)
0.4
0.45
+5
UNIT
mA
mA
µA
MpF
ns
ns
TESTED
*
Electrical Specifications
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
TABLE 1. ISL55211 INTENDED TRANSFORMER + INTERNAL GAIN
SETTINGS
INPUT
XFMR
TURNS
RATIO
1:1.4
R
T
V
O
ISL55211
500
R
G
V
I
1:n
50
INPUT
+
INTERNAL
R
G
VALUE
()
250
125
100
250
125
100
GAIN (V/V)
V
O
/V
I
2.8
5.6
7
4
8
10
GAIN (dB)
V
O
/V
I
9
15
17
12
18
20
R
T
VALUE ()
TO GET 50
MATCH
122
162
192
333
1020
Open
1:1.4
1:1.4
R
G
-
1:2
1:2
1:2
500
FIGURE 2. INTENDED CONFIGURATION
FN7868 Rev 0.00
June 21, 2011
Page 5 of 20
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