eGaN® FET DATASHEET
EPC2024
EPC2024 – Enhancement Mode Power Transistor
V
DSS
, 40 V
R
DS(on)
, 1.5 m
I
D
, 90 A
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally
high electron mobility allows very low R
DS(on)
, while its lateral device structure and majority carrier
diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a device that can handle tasks
where very high switching frequency, and low on-time are beneficial as well as those where on-state
losses dominate.
Maximum Ratings
V
DS
I
D
V
GS
T
J
T
STG
Drain-to-Source Voltage (Continuous)
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
Continuous (T
A
= 25˚C, R
ΘJA
= 6˚C/W)
Pulsed (25˚C, T
PULSE
= 300 µs)
Gate-to-Source Voltage
Gate-to-Source Voltage
Operating Temperature
Storage Temperature
40
48
90
560
6
-4
-40 to 150
-40 to 150
V
A
V
˚C
EFFICIENT POWER CONVERSION
HAL
EPC2024 eGaN® FETs are supplied only in
passivated die form with solder bumps
Die Size: 6.05 mm x 2.3 mm
Applications
• High Frequency DC-DC Conversion
• Motor Drive
• Industrial Automation
• Synchronous Rectification
• Inrush Protection
• Point-of-Load (POL) Converters
www.epc-co.com/epc/Products/eGaNFETs/EPC2024.aspx
Static Characteristics
(T
J
= 25˚C unless otherwise stated)
PARAMETER
BV
DSS
I
DSS
I
GSS
V
GS(TH)
R
DS(on)
V
SD
Drain-to-Source Voltage
Drain Source Leakage
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Threshold Voltage
Drain-Source on Resistance
Source-Drain Forward Voltage
TEST CONDITIONS
V
GS
= 0 V, I
D
= 1.1 mA
V
DS
= 32 V, V
GS
= 0 V
V
GS
= 5 V
V
GS
= -4 V
V
DS
= V
GS
, I
D
= 19 mA
V
GS
= 5 V, I
D
= 37 A
I
S
= 0.5 A, V
GS
= 0 V
0.8
MIN
40
0.1
1
0.1
1.4
1.2
1.8
0.9
9
0.9
2.5
1.5
TYP
MAX
UNIT
V
mA
mA
mA
V
m
V
All measurements were done with substrate shorted to source.
Thermal Characteristics
TYP
R
ΘJC
R
ΘJB
R
ΘJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Board
Thermal Resistance, Junction to Ambient (Note 1)
0.4
1.1
42
UNIT
˚C/W
˚C/W
˚C/W
Note 1: R
ΘJA
is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
EPC – EFFICIENT POWER CONVERSION CORPORATION |
WWW.EPC-CO.COM
| COPYRIGHT 2016 |
| 1
eGaN® FET DATASHEET
Dynamic Characteristics
(T
J
= 25˚C unless otherwise stated)
PARAMETER
C
ISS
C
RSS
C
OSS
C
OSS(ER)
C
OSS(TR)
R
G
Q
G
Q
GS
Q
GD
Q
G(TH)
Q
OSS
Q
RR
Input Capacitance
Reverse Transfer Capacitance
Output Capacitance
E ective Output Capacitance
Energy Related (Note 2)
E ective Output Capacitance, Time
Related (Note 3)
EPC2024
TEST CONDITIONS
V
DS
= 20 V, V
GS
= 0 V
MIN
TYP
1920
29
1620
2050
V
DS
= 0 to 20 V, V
GS
= 0 V
2240
0.3
V
DS
= 20 V, V
GS
= 5 V, I
D
= 37 A
V
DS
= 20 V, I
D
= 37 A
V
DS
= 20 V, V
GS
= 0 V
18
5.1
2.4
3.8
45
0
68
nC
24
2430
pF
MAX
2300
UNIT
Gate Resistance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge at Threshold
Output Charge
Source-Drain Recovery Charge
Note 2: C
OSS(ER)
is a xed capacitance that gives the same stored energy as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.
Note 3: C
OSS(TR)
is a xed capacitance that gives the same charging time as C
OSS
while V
DS
is rising from 0 to 50% BV
DSS
.
Figure 1: Typical Output Characteristics at 25°C
500
V
GS
= 5 V
V
GS
= 4 V
V
GS
= 3 V
V
GS
= 2 V
500
Figure 2: Transfer Characteristics
25°C
125°C
V
DS
= 3 V
I
D
– Drain Current (A)
I
D
– Drain Current (A)
3.0
400
400
300
300
200
200
100
100
0
0
0.5
V
DS
– Drain-to-Source Voltage (V)
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
GS
– Gate-to-Source Voltage (V)
Figure 3: R
DS(on)
vs. V
GS
for Various Drain Currents
R
DS(on)
– Drain-to-Source Resistance (m )
R
DS(on)
– Drain-to-Source Resistance (m )
Figure 4: R
DS(on)
vs. V
GS
for Various Temperatures
25°C
125°C
I
D
= 37 A
3
4
3
I
D
= 35 A
I
D
= 70 A
I
D
= 140 A
I
D
= 210 A
4
2
2
1
1
0
2.5
3.0
V
GS
– Gate-to-Source Voltage (V)
3.5
4.0
4.5
5.0
0
2.5
3.0
V
GS
– Gate-to-Source Voltage (V)
3.5
4.0
4.5
5.0
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| COPYRIGHT 2016 |
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eGaN® FET DATASHEET
Figure 5a: Capacitance (Linear Scale)
3500
3000
2500
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
EPC2024
Figure 5b: Capacitance (Log Scale)
1000
Capacitance (pF)
Capacitance (pF)
2000
1500
1000
500
0
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
100
0
10
V
DS
– Drain-to-Source Voltage (V)
20
30
40
10
0
10
20
30
40
V
DS
– Drain-to-Source Voltage (V)
Figure 6: Gate Charge
5
I
D
= 37 A
V
DS
= 20 V
500
Figure 7: Reverse Drain-Source Characteristics
V
GS
– Gate-to-Source Voltage (V)
I
SD
– Source-to-Drain Current (A)
4
400
25°C
125°C
3
300
2
200
1
100
0
0
5
Q
G
– Gate Charge (nC)
10
15
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
SD
– Source-to-Drain Voltage (V)
Figure 8: Normalized On-State Resistance vs. Temperature
2.0
1.4
I
D
= 37 A
V
GS
= 5 V
1.3
Figure 9: Normalized Threshold Voltage vs. Temperature
I
D
= 19 mA
Normalized On-State Resistance – R
DS(on)
1.8
1.6
1.4
1.2
1.0
0.8
Normalized Threshold Voltage
50
75
100
125
150
1.2
1.1
1.0
0.9
0.8
0.7
0
25
0.6
T
J
– Junction Temperature (ºC)
0
25
T
J
– Junction Temperature (ºC)
50
75
100
125
150
All measurements were done with substrate shortened to source.
T
J
= 25°C unless otherwise stated
EPC – EFFICIENT POWER CONVERSION CORPORATION |
WWW.EPC-CO.COM
| COPYRIGHT 2016 |
| 3
eGaN® FET DATASHEET
Figure 10: Gate Leakage Current
80
EPC2024
60
I
G
– Gate Current (mA)
25°C
125°C
40
20
0
0
1
2
3
4
5
6
V
GS
– Gate-to-Source Voltage (V)
Figure 11: Transient Thermal Response Curves
Duty Factors:
1
0.5
Z
θJB
, Normalized Thermal Impedance
0.1
0.01
0.001
0.0001
0.1
0.05
0.02
0.01
Transient Thermal Response Curves (Junction-to-Board)
P
DM
t
1
t
2
Single Pulse
Notes:
Duty Factor: D = t
1
/t
2
Peak T
J
= P
DM
x Z
θJB
x R
θJB
+ T
B
10
-4
10
-3
10
-2
10
-1
1
10
10
-5
t
p
, Rectangular Pulse Duration, seconds
Z
θJC
, Normalized Thermal Impedance
Duty Factors:
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
Single Pulse
0.001
0.0001
Transient Thermal Response Curves (Junction-to-Case)
P
DM
t
1
Notes:
Duty Factor: D = t
1
/t
2
Peak T
J
= P
DM
x Z
θJC
x R
θJC
+ T
B
t
2
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
1
t
p
, Rectangular Pulse Duration, seconds
EPC – EFFICIENT POWER CONVERSION CORPORATION |
WWW.EPC-CO.COM
| COPYRIGHT 2016 |
| 4
eGaN® FET DATASHEET
Figure 12: Safe Operating Area
EPC2024
1000
100
Limited by R
DS(on)
I
D
–
Drain Current (A)
10
1
Pulse Width
100 ms
10 ms
1 ms
100 µs
0.1
1
10
100
0.1
V
DS
– Drain Voltage (V)
TAPE AND REEL CONFIGURATION
4mm pitch, 8mm wide tape on 7” reel
b
d
e
f
g
Loaded Tape Feed Direction
7” reel
Die
orientation
dot
Dimension (mm) target min
EPC2024 (note 1)
12.00
1.75
5.50
4.00
4.00
2.00
1.50
11.70
1.65
5.45
3.90
3.90
1.95
1.50
a
b
c (see note)
d
e
f (see note)
g
12.30
1.85
5.55
4.10
4.10
2.05
1.60
max
Die is placed into pocket
solder bar side down
(face side down)
Note 1: MSL 1 (moisture sensitivity level 1) classi ed according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
DIE MARKINGS
2024
Die orientation dot
Gate Pad bump is
under this corner
YYYY
ZZZZ
Part
Number
EPC2024
Laser Marking
Part #
Marking Line 1
2024
Lot_Date Code
Marking Line 2
YYYY
Lot_Date Code
Marking Line 3
ZZZZ
EPC – EFFICIENT POWER CONVERSION CORPORATION |
WWW.EPC-CO.COM
| COPYRIGHT 2016 |
YYYY
2024
a
c
ZZZZ
Gate
solder bar is
under this
corner
| 5
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