DATASHEET
ISLA222P
Dual 12-Bit, 250MSPS/200MSPS/130MSPS ADC
The ISLA222P is a family of dual-channel 12-bit
analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the family supports sampling rates of up to
250MSPS. The ISLA222P is part of a pin-compatible portfolio
of 12-bit and 14-bit dual-channel A/Ds with maximum sample
rates ranging from 130MSPS to 250MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA222P is available in a 72 lead QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
FN7853
Rev 1.00
June 17, 2011
Features
• Single Supply 1.8V Operation
• Clock Duty Cycle Stabilizer
• 75fs Clock Jitter
• 700MHz Bandwidth
• Programmable Built-in Test Patterns
• Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
• Nap and Sleep Modes
- 200µs Sleep Wake-up Time
• Data Output Clock
• DDR LVDS-Compatible or LVCMOS Outputs
• User-accessible Digital Temperature Monitor
Key Specifications
• SNR @ 250/200/130MSPS
70.3/71.0/71.3dBFS f
IN
= 30MHz
68.5/68.8/68.4dBFS f
IN
= 363MHz
• SFDR @ 250/200/130MSPS
85/87/86dBc f
IN
= 30MHz
73/75/80dBc f
IN
= 363MHz
• Total Power Consumption = 823mW @ 250MSPS
Applications
• Radar Array Processing
• Software Defined Radios
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
CLKDIVRSTN
CLKDIVRSTP
Pin-Compatible Family
MODEL
CLKOUTP
CLKOUTN
CLKDIV
RESOLUTION
14
14
12
12
12
SPEED
(MSPS)
200
130
250
200
130
OVDD
AVDD
CLKP
CLKN
CLOCK
MANAGEMENT
ISLA224P20
ISLA224P13
ISLA222P25
ISLA222P20
ISLA222P13
VINBP
VINBN
SHA
12-BIT
250 MSPS
ADC
VREF
DIGITAL
ERROR
CORRECTION
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
VCM
VINAN
VINAP
SHA
12-BIT
250 MSPS
ADC
VREF
+
1.25V
-
–
SPI
CONTROL
RESETN
CSB
SCLK
SDIO
SDO
Pin-Compatible Family
MODEL
ISLA224P25
RESOLUTION
14
SPEED
(MSPS)
250
FN7853 Rev 1.00
June 17, 2011
NAPSLP
OVSS
AVSS
Page 1 of 33
ISLA222P
Pin Configuration - LVDS Mode
ISLA222P
(72 LD QFN)
TOP VIEW
OVDD
OVSS
OVSS
AVDD
AVDD
AVDD
SCLK
SDIO
ORN
DNC
DNC
DNC
DNC
ORP
SDO
CSB
D0N
55
54 D1P
53 D1N
52 D2P
51 D2N
50 D3P
49 D3N
48 CLKOUTP
47 CLKOUTN
46 RLVDS
45 OVSS
44 D4P
43 D4N
42 D5P
41 D5N
40 D6P
Thermal Pad Not Drawn to Scale.
Consult Mechanical Drawing for
Physical Dimensions
39 D6N
Connect Thermal Pad to AVSS
38 D7P
37 D7N
19
AVDD
20
AVDD
21
AVDD
22
CLKP
23
CLKN
24
CLKDIVRSTP
25
CLKDIVRSTN
26
OVSS
27
OVDD
28
D11N
29
D11P
30
D10N
31
D10P
32
OVDD
33
D9N
34
D9P
35
D8N
36
D8P
D0P
56
72
DNC
DNC
NAPSLP
VCM
AVSS
VINBP
VINBN
AVSS
AVDD
1
2
3
4
5
6
7
8
9
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
AVDD 10
AVSS 11
VINAN 12
VINAP 13
AVSS 14
CLKDIV 15
IPTAT 16
DNC 17
RESETN 18
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
1, 2, 17, 57, 58, 59, 60
9, 10, 19, 20, 21, 70, 71, 72
5, 8, 11, 14
27, 32, 62
26, 45, 61, 65
3
4
6, 7
12, 13
LVDS PIN NAME
DNC
AVDD
AVSS
OVDD
OVSS
NAPSLP
VCM
VINBP, VINBN
VINAN, VINAP
Do Not Connect
1.8V Analog Supply
Analog Ground
1.8V Output Supply
Output Ground
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
Channel B Analog Input Positive, Negative
Channel A Analog Input Negative, Positive
LVDS PIN FUNCTION
FN7853 Rev 1.00
June 17, 2011
Page 2 of 33
ISLA222P
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
15
16
18
22, 23
24, 25
28, 29
30, 31
33, 34
35, 36
37, 38
39, 40
41, 42
43, 44
46
47, 48
49, 50
51, 52
53, 54
55, 56
63, 64
66
67
68
69
Exposed Paddle
LVDS PIN NAME
CLKDIV
IPTAT
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D11N, D11P
D10N, D10P
D9N, D9P
D8N, D8P
D7N, D7P
D6N, D6P
D5N, D5P
D4N, D4P
RLVDS
CLKOUTN, CLKOUTP
D3N, D3P
D2N, D2P
D1N, D1P
D0N, D0P
ORN, ORP
SDO
CSB
SCLK
SDIO
AVSS
(Continued)
LVDS PIN FUNCTION
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
LVDS Bit 11 (MSB) Output Complement, True
LVDS Bit 10 Output Complement, True
LVDS Bit 9 Output Complement, True
LVDS Bit 8 Output Complement, True
LVDS Bit 7 Output Complement, True
LVDS Bit 6 Output Complement, True
LVDS Bit 5 Output Complement, True
LVDS Bit 4 Output Complement, True
LVDS Bias Resistor (connect to OVSS with 1% 10k)
LVDS Clock Output Complement, True
LVDS Bit 3 Output Complement, True
LVDS Bit 2 Output Complement, True
LVDS Bit 1 Output Complement, True
LVDS Bit 0 (LSB) Output Complement, True
LVDS Over Range Complement, True
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
FN7853 Rev 1.00
June 17, 2011
Page 3 of 33
ISLA222P
Pin Configuration - CMOS Mode
ISLA222P
(72 LD QFN)
TOP VIEW
OVDD
OVSS
OVSS
AVDD
AVDD
AVDD
SCLK
SDIO
SDO
DNC
DNC
DNC
DNC
DNC
DNC
55
54 D1
53 DNC
52 D2
51 DNC
50 D3
49 DNC
48 CLKOUT
47 DNC
46 RLVDS
45 OVSS
44 D4
43 DNC
42 D5
41 DNC
40 D6
Thermal Pad Not Drawn to Scale.
Consult Mechanical Drawing for
Physical Dimensions
39 DNC
Connect Thermal Pad to AVSS
38 D7
37 DNC
19
AVDD
20
AVDD
21
AVDD
22
CLKP
23
CLKN
24
CLKDIVRSTP
25
CLKDIVRSTN
26
OVSS
27
OVDD
28
DNC
29
D11
30
DNC
31
D10
32
OVDD
33
DNC
34
D9
35
DNC
36
D8
CSB
OR
D0
56
72
DNC
DNC
NAPSLP
VCM
AVSS
VINBP
VINBN
AVSS
AVDD
AVDD
AVSS
VINAN
VINAP
AVSS
CLKDIV
IPTAT
DNC
RESETN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
1, 2, 17, 28, 30, 33, 35, 37, 39,
41, 43, 47, 49, 51, 53, 55, 57,
58, 59, 60, 63
9, 10, 19, 20, 21, 70, 71, 72
5, 8, 11, 14
27, 32, 62
26, 45, 61, 65
3
4
CMOS PIN NAME
DNC
Do Not Connect
CMOS PIN FUNCTION
AVDD
AVSS
OVDD
OVSS
NAPSLP
VCM
1.8V Analog Supply
Analog Ground
1.8V Output Supply
Output Ground
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
FN7853 Rev 1.00
June 17, 2011
Page 4 of 33
ISLA222P
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
6, 7
12, 13
15
16
18
22, 23
24, 25
29
31
34
36
38
40
42
44
46
48
50
52
54
56
64
66
67
68
69
Exposed Paddle
CMOS PIN NAME
VINBP, VINBN
VINAN, VINAP
CLKDIV
IPTAT
RESETN
CLKP, CLKN
CLKDIVRSTP, CLKDIVRSTN
D11
D10
D9
D8
D7
D6
D5
D4
RLVDS
CLKOUT
D3
D2
D1
D0
OR
SDO
CSB
SCLK
SDIO
AVSS
(Continued)
CMOS PIN FUNCTION
Channel B Analog Input Positive, Negative
Channel A Analog Input Negative, Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
CMOS Bit 11 (MSB) Output
CMOS Bit 10 Output
CMOS Bit 9 Output
CMOS Bit 8 Output
CMOS Bit 7 Output
CMOS Bit 6 Output
CMOS Bit 5 Output
CMOS Bit 4 Output
LVDS Bias Resistor (connect to OVSS with 1% 10k)
CMOS Clock Output
CMOS Bit 3 Output
CMOS Bit 2 Output
CMOS Bit 1 Output
CMOS Bit 0 (LSB) Output
CMOS Over Range
SPI Serial Data Output
SPI Chip Select (active low)
SPI Clock
SPI Serial Data Input/Output
Analog Ground
FN7853 Rev 1.00
June 17, 2011
Page 5 of 33
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
