DEMO MANUAL DC1813A
LTC2370/LTC2369/LTC2368/
LTC2367/LTC2364: 18-Bit/16-Bit, 2Msps/1.6Msps/1Msps/
500ksps/250ksps Low Power, Low Noise ADCs
Description
The LTC
®
2370/LTC2369/LTC2368/LTC2367/LTC2364 are
low power, low noise ADCs with serial outputs that can
operate from a single 2.5V supply. The following text refers
to the LTC2369-18 but applies to all parts in the family,
the only difference being the maximum sample rates and
the number of bits. The LTC2369-18 supports a 0V to 5V
pseudo-differential input range with a 96dB SNR, consumes
only 18mW and achieves ±2LSB INL max with no missing
codes at 18-bits. The DC1813A demonstrates the DC and
AC performance of the LTC2369-18 in conjunction with the
DC590 QuikEval™ and DC718 QuikEval II data collection
boards. Use the DC590 to demonstrate DC performance
such as peak-to-peak noise and DC linearity. Use the DC718
if precise sampling rates are required or to demonstrate
AC performance such as SNR, THD, SINAD and SFDR.
The DC1813A is intended to demonstrate recommended
grounding, component placement and selection, routing
and bypassing for this ADC. Several suggested driver
circuits for the analog inputs will be presented.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
QuikEval and PScope is a trademark of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
BoarD photo
–9V
GND
+9V
CLK IN
100MHz MAX
3.3V
P-P
MAX
TO DC718C
A
IN
+
0V TO V
REF
MAX
A
IN
–
0V TO V
REF
MAX
TO DC590B
DC1813A F01
Figure 1. DC1813A Connection Diagram
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DEMO MANUAL DC1813A
Quick start proceDure
Check to make sure that all switches and jumpers are
set as shown in the connection diagram of Figure 1. The
default connections configure the ADC to use the onboard
reference and regulators to generate the required common
mode voltages. The analog input is DC-coupled. Connect
the DC1813A to a DC718 USB high speed data collection
board using connector J2. Then, connect the DC718 to a
host PC with a standard USB A/B cable. Apply ±9V to the
indicated terminals. Then apply a low jitter signal source
to J4. Connect a low jitter 99.2MHz 3.3V
P-P
sine wave
or square wave to connector J1. Note that J1 has a 50Ω
termination resistor to ground.
Run the QuickEval II software (PScope.exe version K72
or later) supplied with the DC718 or download it from
www.linear.com.
Complete software documentation is available from the
Help menu. Updates can be downloaded from the Tools
menu. Check for updates periodically as new features
may be added.
The PScope™ software should recognize the DC1813A
and configure itself automatically.
Click the Collect button (See Figure 6) to begin acquiring
data. The Collect button then changes to Pause, which
can be clicked to stop data acquisition.
Table 1. Assembly Options
ASSEMBLY VERSION
DC1813A-A
DC1813A-B
DC1813A-C
DC1813A-D
DC1813A-E
DC1813A-F
DC1813A-G
DC1813A-H
U1 PART NUMBER
LTC2370CMS-16
LTC2368CMS-16
LTC2367CMS-16
LTC2364CMS-16
LTC2369CMS-18
LTC2368CMS-18
LTC2367CMS-18
LTC2364CMS-18
MAX CONVERSION RATE
2Msps
1Msps
500ksps
250ksps
1.6Msps
1Msps
500ksps
250ksps
NUMBER OF BITS
16
16
16
16
18
18
18
18
MAX CLK IN FREQUENCY
100MHz
50MHz
25MHz
12.5MHz
99.2MHz
62MHz
31MHz
15.5MHz
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DEMO MANUAL DC1813A
Dc590 setup
IMPORTANT! To avoid damage to the DC1813A, make
sure that VCCIO (JP6 of the DC590) is set to 3.3V before
connecting the DC590 to the DC1813A.
To use the DC590 with the DC1813A, it is necessary to
apply –9V and ground to the –9V and GND terminals or
disable amplifier U15 by moving R32 and R36 to R31 and
R38 respectively. Connect the DC590 to a host PC with a
standard USB A/B cable. Connect the DC1813A to a DC590
USB serial controller using the supplied 14-conductor
ribbon cable. Apply a signal source to J4 or J4 and J8
depending on how the DC1813A is configured.
Run the evaluation software supplied with the DC590 or
download it from
www.linear.com.
The correct control
panel will be loaded automatically. Click the Collect button
(Figure 7) to begin reading the ADC.
Dc1813a setup
DC Power
The DC1813A requires ±9V
DC
and draws 50mA. Most of
the supply current is consumed by the CPLD, op amps,
regulators and discrete logic on the board. The 9V
DC
in-
put voltage powers the ADC through LT1763 regulators
which provide protection against accidental reverse bias.
Additional regulators provide power for the CPLD and op
amps. See Figure 1 for connection details.
Clock Source
You must provide a low jitter 3.3V
P-P
sine or square wave
to J1. The clock input is AC-coupled so the DC level of the
clock signal is not important. A generator like the HP8644
or the DC1216A-A is recommended. Even a good generator
can start to produce noticeable jitter at low frequencies.
Therefore it is recommended for lower sample rates to
divide down a higher frequency clock to the desired sample
rate. The ratio of clock frequency to conversion rate is
62:1 for 18-bit parts and 50:1 for 16-bit parts. If the clock
input is to be driven with logic, it is recommended that the
50Ω terminator (R5) be removed. Slow rising edges may
compromise the SNR of the converter in the presence of
high amplitude higher frequency input signals.
Data Output
Parallel data output from this board (0V to 3.3V default),
if not connected to the DC718, can be acquired by a logic
analyzer, and subsequently imported into a spreadsheet, or
mathematical package depending on what form of digital
signal processing is desired. Alternatively, the data can be
fed directly into an application circuit. Use Pin 3 of J2 to
latch the data. The data can be latched using either edge
of this signal. The data output signal levels at J2 can also
be reduced to 0V to 2.5V if the application circuit cannot
tolerate the higher voltage. This is accomplished by mov-
ing JP3 to the 2.5V position.
Reference
The default reference is a LTC6655 5V reference. Alterna-
tively, if a lower power reference is desired, this reference
(U20) can be removed and a LTC6652 5V reference can
be installed in the U10 position. This will result in only
a small loss in performance in applications where the
ADC is continuously converting. If an external reference
is used it must settle quickly in the presence of glitches
on the REF pin.
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DEMO MANUAL DC1813A
Dc1813a setup
Analog Input
The default driver for the analog inputs of the LTC2369-18
on the DC1813A is shown in Figure 2. This circuit band
limits the input frequencies to approximately 800kHz.
Alternatively, if you need to level shift the input signal,
the circuit shown in Figure 3 can be used. The circuit in
Figure 3 AC couples the input signal and is usable down
to about 10kHz. The lower frequency limit can be extended
by increasing C17.
AC-coupling the input may degrade the distortion per-
formance of the ADC due to nonlinearity of the coupling
capacitor (C17). The circuit in Figure 3 can be implemented
on the DC1813A by putting JP1 in the AC position and
adding a 1kΩ resistor at the R9 location.
One of the most asked for ADC driver circuits is one that
allows the input voltage to swing below ground while using
a single supply ADC. The input driver shown in Figure 4
accepts a true bipolar input voltage range of ±10V and
converts it to the 0V to 5V input swing of the ADC. The
circuit of Figure 4 can be implemented on the DC1813A
by replacing R9 with 499Ω, R15 with 2kΩ, R35 with 2kΩ
and R45 with 499Ω.
Data Collection
For SINAD, THD or SNR testing a low noise, low distortion
generator such as the B&K Type 1051 or Stanford Research
DS360 should be used. A low jitter RF oscillator such as
the HP8644 or DC1216A-A is used as the clock source.
This demo board is tested in house by attempting to dupli-
cate the FFT plot shown on the front page of the LTC2369-18
data sheet. This involves using a 100MHz clock source,
along with a sinusoidal generator at a frequency of 2.0kHz.
The input signal level is approximately –1dBfs. The input is
level shifted and filtered with the circuit shown in Figure 5.
A typical FFT obtained with DC1813A is shown in Figure 6.
Note that to calculate the real SNR, the signal level (F1
amplitude = –1.037dB) has to be added back to the SNR
that PScope (QuikEval II) displays. With the example
shown in Figure 6 this means that the actual SNR would
be 96.46dB instead of the 95.43dB that PScope displays.
Taking the RMS sum of the recalculated SNR and the THD
yields a SINAD of 96.16 dB which is fairly close to the
typical number for this ADC.
There are a number of scenarios that can produce mis-
leading results when evaluating an ADC. One that is
common is feeding the converter with a frequency, that
is a sub-multiple of the sample rate, and which will only
exercise a small subset of the possible output codes.
The proper method is to pick an M/N frequency for the
input sine wave frequency. N is the number of samples
in the FFT. M is a prime number between one and N/2.
Multiply M/N by the sample rate to obtain the input sine
wave frequency. Another scenario that can yield poor
results is if you do not have a signal generator capable of
ppm frequency accuracy or if it cannot be locked to the
clock frequency. You can use an FFT with windowing to
reduce the “leakage” or spreading of the fundamental, to
get a close approximation of the ADC performance. If an
amplifier or clock source with poor phase noise is used,
the windowing will not improve the SNR.
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DEMO MANUAL DC1813A
Dc1813a setup
A
IN
0V TO V
REF
+
LT6202
R32
5.1
R58
0
C39
0.01µF
NPO
R16
0
R19
0
+
LTC2369-18
–
–
DC1813A F02
Figure 2. DC-Coupled LT6202 Driver
V
REF
/2
C17
10µF
A
IN
0V TO V
REF
R9
1k
+
LT6202
R32
5.1
R58
0
C39
0.01µF
NPO
R16
0
R19
0
+
LTC2369-18
–
–
DC1813A F03
Figure 3. AC-Coupled LT6202 Driver
V
REF
/2
R9
499Ω
R15
2k
C39
0.01µF
NPO
+
LT6202
R32
5.1
R58
0
R16
0
R19
0
–
R45
499
DC1813A F04
0V TO 5V
TO IN
+
A
IN
10V TO –10V
R35
2k
TO IN
–
Figure 4. ±10V Into 0V to 5V DC-Coupled Driver
V
REF
1k
A
IN
+
0.15µF
DC1813A F05
SINE IN
–V
REF
TO V
REF
1k
Figure 5. Level Shift and Filter Circuit Used for Board Testing
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