ISL6532C
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
FN9121
Rev 2.00
Jul 2004
ACPI Regulator/Controller for Dual Channel DDR Memory Systems
The ISL6532C provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply V
DDQ
with high current during
S0/S1 states and standby current during S3 state. During
S0/S1 state, a fully integrated sink-source regulator
generates an accurate (V
DDQ
/2) high current V
TT
voltage
without the need for a negative supply. A buffered version of
the V
DDQ
/2 reference is provided as V
REF
. An LDO
controller is also integrated for AGP core voltage regulation.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. Both the switching
regulator and standby LDO provide a maximum static
regulation tolerance of
2% over line, load, and temperature
ranges. The output is user-adjustable by means of external
resistors down to 0.8V.
Switching memory core output between the PWM regulator
and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the PGOOD signal
indicates V
TT
is within spec and operational.
Each output is monitored for under and over-voltage events.
The switching regulator has over current protection. Thermal
shutdown is integrated.
Features
• Generates 3 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference.
- Glitch-free Transitions During State Changes
- LDO Regulator for 1.5V Video and Core voltage
• ACPI compliant sleep state control
• Integrated V
REF
Buffer
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- All Outputs:
2% Over Temperature
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Over-voltage Monitoring on All Outputs
• OCP on the Switching Regulator and V
TT
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-free available
Pinout
ISL6532C (QFN)
TOP VIEW
UGATE
LGATE
GNDP
P12V
NCH
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
• Graphics cards - GPU and memory supplies
21 PGOOD
20 PHASE
19 DRIVE2
18 FB2
17 GNDA
16 COMP
15 FB
S5#
28 27 26 25 24 23 22
GNDP 1
5VSBY 2
GNDQ 3
GNDQ 4
VTT 5
VTT 6
VDDQ 7
8
VDDQ
9
VDDQ
10 11 12 13 14
VREF_OUT
VREF_IN
P5VSBY
VTTSNS
OCSET
S3#
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP. RANGE
PART NUMBER
(
o
C)
ISL6532CCR
ISL6532CCRZ
(See Note)
0 to 70
0 to 70
PACKAGE
PKG. DWG. #
28 Ld 6x6 QFN L28.6x6
28 Ld 6x6 QFN L28.6x6
(Pb-free)
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
FN9121 Rev 2.00
Jul 2004
Page 1 of 16
ISL6532C
Absolute Maximum Ratings
5VSBY, P5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
UGATE, LGATE, NCH . . . . . . . . . . . . . . GND - 0.3V to P12V + 0.3V
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Thermal Information
Thermal Resistance (Typical, Notes 1, 2)
JA
(
o
C/W)
JC
(
o
C/W)
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V
10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V
10%
Supply Voltage on P5VSBY. . . . . . . . . . . . . . . . . . . . . . . +5V
10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Junction Temperature Range . . . . . . . . . . . . . . . . . . 0
o
C to 125
o
C
QFN Package . . . . . . . . . . . . . . . . . . .
32
5
Maximum Junction Temperature (Plastic Package) . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
5VSBY SUPPLY CURRENT
Nominal Supply Current
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
CC_S0
I
CC_S3
I
CC_S5
S3# & S5# HIGH, UGATE/LGATE Open
S3# LOW, S5# HIGH, UGATE/LGATE
Open
S5# LOW, S3# Don’t Care,
UGATE/LGATE Open
3.00
3.50
300
5.25
-
-
7.25
4.75
800
mA
mA
A
POWER-ON RESET
Rising 5VSBY POR Threshold
Falling 5VSBY POR Threshold
Rising P12V POR Threshold
Falling P12V POR Threshold
OSCILLATOR AND SOFT-START
PWM Frequency
Ramp Amplitude
Error Amp Reset Time
VDDQ Soft-Start Interval
REFERENCE VOLTAGE
Reference Voltage
System Accuracy
PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
STATE LOGIC
S3# Transition Level
S5# Transition Level
V
S3
V
S5
-
-
1.5
1.5
-
-
V
V
GBWP
SR
Guaranteed By Design
-
15
-
80
-
6
-
-
-
dB
MHz
V/s
V
REF
-
-2.0
0.800
-
-
+2.0
V
%
f
OSC
V
OSC
t
RESET
t
SS
Mechanical Off/S5 to S0
Mechanical Off/S5 to S0
220
-
6.5
6.5
250
1.5
-
-
280
-
9.5
9.5
kHz
V
ms
ms
4.00
3.60
10.0
8.80
-
-
-
-
4.35
3.95
10.5
9.75
V
V
V
V
FN9121 Rev 2.00
Jul 2004
Page 5 of 16
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