®
ISL6260, ISL6260B
Data Sheet
January 3, 2006
FN9162.1
Multiphase Core Regulator for IMVP-6
Mobile CPUs
The ISL6260 and ISL6260B provide microprocessor core
voltage regulation by driving up to 3 channels in parallel. The
multiphase buck converter architecture uses interleaved
channels to multiply the output voltage ripple frequency and
reduce output channel currents. The reduction in ripple results
in fewer components, lower component cost, reduced power
dissipation, and smaller implementation area. The ISL6260,
ISL6260B multiphase controller together with the ISL6208 gate
drivers form the basis for a portable power supply solution to
power Intel's next generation mobile microprocessors. The
modulator at the heart of this power system is derived from
Intersil's Robust Ripple Regulator technology, (R
3
) Compared
with the traditional multiphase buck regulator, the R
3
technology multiphase converter has faster transient response.
This is due to the R
3
modulator commanding variable switching
frequency during load transients.
Intel Mobile Voltage Positioning is a smart voltage regulation
technology, which effectively reduces power dissipation in Intel
Pentium processors. The ISL6260 and ISL6260B support the
IMVP-6 mobile processor voltage regulation specifications.
ISL6260 and ISL6260B are pin-to-pin compatible. ISL6260B
responds to PSI# signal by adding or dropping PWM2 and
adjusting overcurrent protection accordingly. To improve
audible noise, the DPRSLPVR signal can be used to reduce
slew rates entering and exiting Deeper Sleep.
The ISL6260 and ISL6260B have several other key features.
Current sensing can be done using either DCR sensing or
discrete precision resistor sensing. A single NTC thermistor
thermally compensates both the gain and time constant of
the DCR variation. A unity gain, differential amplifier is
provided for remote CPU die sensing. This allows the
voltage on the CPU die to be accurately measured and
regulated per Intel IMVP-6 specifications.
Features
• Precision Multiphase Core Voltage Regulation
- 0.5% System Accuracy Over Temperature
- Enhanced Load Line Accuracy
• Microprocessor Voltage Identification Input
- 7-Bit VID Input
- 0.300V to 1.500V in 12.5mV Steps
- Supports VID Changes On-The-Fly
• Multiple Current Sensing Approaches Supported
- Lossless DCR Current Sensing
- Precision Resistive Current Sensing
• Supports PSI# and Narrow VDC for Enhanced Battery Life
(EBL) Initiatives
• Superior Noise Immunity and Transient Response
• Thermal Monitor
• Differential Remote Voltage Sensing
• High Efficiency Across Entire Load Range
• Programmable 1, 2 or 3 Power Channels
• Balanced Channel Loading Including Transients
• Small Footprint QFN 40 Lead 6x6 Package
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Mobile laptop computers
Pinout
ISL6260CRZ, ISL6260BCRZ (QFN)
TOP VIEW
DPRSTP#
CLK_EN#
PGOOD
DPRSLPVR
VR_ON
VID6
VID5
VID4
40
PSI# 1
PGD_IN 2
RBIAS 3
39
3V3
38
37
36
35
34
33
32
31
30 VID2
29 VID1
28 VID0
27 PWM1
Ordering Information
PART NUMBER
(Note)
ISL6260CRZ
ISL6260CRZ-T
ISL6260BCRZ
PART
MARKING
ISL6260CRZ
ISL6260CRZ
TEMP.
RANGE
(°C)
PACKAGE
(Pb-FREE)
PKG.
DWG. #
VR_TT# 4
NTC 5
SOFT 6
OCSET 7
VW 8
COMP 9
FB 10
11
VDIFF
VID3
GND PAD
(BOTTOM)
26 PWM2
25 PWM3
24 FCCM
23 ISEN1
22 ISEN2
21 ISEN3
-10 to 100 40 Ld 6x6 QFN L40.6x6
-10 to 100 40 Ld 6x6 QFN L40.6x6
ISL6260BCRZ -10 to 100 40 Ld 6x6 QFN L40.6x6
ISL6260BCRZ-T ISL6260BCRZ -10 to 100 40 Ld 6x6 QFN L40.6x6
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
12
VSEN
13
RTN
14
DROOP
15
DFB
16
VO
17
VSUM
18
VIN
19
VSS
20
VDD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6260, ISL6260B
Functional Pin Description
DPRSLPVR
DPRSTP#
CLK_EN#
PGOOD
VR_ON
VID6
VID5
VID4
VID3
3V3
VW
A resistor from this pin to COMP programs the switching
frequency. (7kΩ gives approximately 300kHz). VW pin
sources current.
40
PSI# 1
PGD_IN 2
RBIAS 3
VR_TT# 4
NTC 5
SOFT 6
OCSET 7
VW 8
COMP 9
FB 10
11
VDIFF
39
38
37
36
35
34
33
32
31
30 VID2
29 VID1
28 VID0
27 PWM1
COMP
This pin is the output of the error amplifier.
FB
This pin is the inverting input of error amplifier.
VDIFF
This pin is the output of the differential amplifier.
GND PAD
(BOTTOM)
26 PWM2
VSEN
25 PWM3
24 FCCM
23 ISEN1
22 ISEN2
21 ISEN3
Remote core voltage sense input. Connect to micro-
processor die.
RTN
Remote voltage sensing return. Connect to ground at micro-
processor die.
DROOP
12
VSEN
13
RTN
14
DROOP
15
DFB
16
VO
17
VSUM
18
VIN
19
VSS
20
VDD
Output of droop amplifier. Output = VO + DROOP.
DFB
Inverting input to droop amplifier.
PSI#
Low load current indicator input. When asserted low,
indicates a reduced load-current condition. For ISL6260B,
when PSI# is asserted low, PWM2 will be disabled.
VO
An input to the IC that reports the local output voltage.
VSUM
This pin is connected to the current summation junction.
PGD_IN
Digital Input. When asserted high, indicates VCCP and
VCC_MCH voltages are within regulation. PGD_IN signal
high is needed for the CLK_EN# to be low and PGOOD to
be high.
VIN
Battery supply voltage, used for feed forward.
VSS
Signal ground; Connect to local controller ground.
RBIAS
147K Resistor to VSS sets internal current reference.
VDD
5V bias power.
VR_TT#
Thermal overload output indicator.
ISEN3
Individual current sensing for channel 3.
NTC
Thermistor input to VRTT# circuit.
ISEN2
Individual current sensing for channel 2.
SOFT
A capacitor from this pin to Vss sets the maximum slew rate
of the output voltage. Soft pin is the non-inverting input of the
error amplifier.
ISEN1
Individual current sensing for channel 1.
FCCM
Forced Continuous Conduction Mode (FCCM) enable pin to
MOSFET drivers. It will disable diode emulation.
OCSET
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
PWM3
PWM output for channel 3.
2
FN9162.1
January 3, 2006
ISL6260, ISL6260B
PWM2
PWM output for channel 2. For ISL6260B, PSI# low will
make this output tri-state.
VR_ON
Voltage Regulator enable input. A high level logic signal on
this pin enables the regulator.
PWM1
PWM output for channel 1.
DPRSLPVR
Deeper Sleep Enable signal. A high level logic signal on this
pin indicates that the micro-processor is in Deeper Sleep
Mode and indicates that slow entry and exit from C4 should
occur. DPRSLPVR low indicates large charging or
discharging soft pin current, and therefore fast output
voltage transitions.
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VID input with VID0 = LSB.
CLK_EN#
Digital output to enable System PLL Clock; Goes active
10µs after PG_IN is active and Vcore is within 10% of Boot
Voltage.
DPRSTP#
Deeper Sleep Enable signal. A low level logic signal on this
pin indicates that the micro-processor is in Deeper Sleep
Mode.
PGOOD
Power Good open-drain output. Will be pulled up externally
by a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
3V3
3.3V supply voltage for CLK_EN# logic, such an
implementation will improve power consumption from 3.3V
compared to open drain circuit other wise.
3
FN9162.1
January 3, 2006
ISL6260, ISL6260B
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 - +7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . . -0.3 - +7V
ALL OTHER PINS . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Thermal Information
θ
JA
(°C/W)
θ
JC
(°C/W)
QFN Package (Notes 1, 2) . . . . . . . . .
30
5.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . +300°C
Thermal Resistance
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 100°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . . +5V ±5%
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
INPUT POWER SUPPLY
+5V Supply Current
Operating Conditions: VDD = 5V, T
A
= -10°C to +100°C, unless otherwise noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
VDD
VR_ON = 3.3V
VR_ON = 0V
2.9
3.5
1
1
1
mA
µA
µA
µA
kΩ
+3.3V Supply Current
Battery Supply Current
VIN Input Resistance
Power-On-Reset Threshold
I
3V3
I
VIN
R
VIN
POR
r
POR
f
No load on CLK_EN#
VR_ON = 0V
VR_ON = 3.3V
V
DD
rising
V
DD
falling
4.00
900
4.35
4.15
4.5
V
V
SYSTEM AND REFERENCES
System Accuracy
%Error
(V
CC_CORE
)
No load; closed loop, active mode range
VID = 0.75V - 1.50V
VID = 0.5V - 0.7375V
VID = 0.3 - 0.4875V
V
BOOT
Maximum Output Voltage
Minimum Output Voltage
VID Off State
R
BIAS
Voltage
CHANNEL FREQUENCY
Nominal Channel Frequency
Adjustment Range
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain
Error Amp Gain-Bandwidth Product
FB Input Current
A
v0
GBW
I
IN(FB)
C
L
= 20pF
-0.3
90
18
10
150
+0.3
mV
dB
MHz
nA
f
SW(nom)
Rfset = 7kΩ, 3 channel operation, Vcomp = 2V
See Equation 4 Rfset selection
285
200
300
315
500
kHz
kHz
V
CC_CORE(max)
VID = [0000000]
V
CC_CORE(min)
VID = [1100000]
VID = [1111111]
R
BIAS
= 147kΩ
1.45
-0.5
-8
-15
1.176
1.200
1.500
0.300
0.0
1.47
1.49
+0.5
+8
+15
1.224
%
mV
mV
V
V
V
V
V
4
FN9162.1
January 3, 2006
ISL6260, ISL6260B
Electrical Specifications
PARAMETER
ISEN
Imbalance Voltage
Input Bias Current
SOFT CURRENT
Soft-start current
SOFT Geyserville Current
SOFT Deeper Sleep Entry Current
SOFT Deeper Sleep Exit Current
SOFT Deeper Sleep Exit Current
I
SS
I
GV
I
C4
I
C4EA
I
C4EB
|SOFT-V
DAC
| >100mV
DPRSLPVR = 3.3V
DPRSLPVR = 3.3V
DPRSLPVR = 0V
-46
±175
-46
36
175
-41
±200
-41
41
200
-36
±225
-36
46
225
μA
μA
μA
μA
μA
Maximum of ISENs - Minimum of ISENs
20
2
mV
nA
Operating Conditions: VDD = 5V, T
A
= -10°C to +100°C, unless otherwise noted.
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
PGOOD Leakage Current
PGOOD Delay
Overvoltage Threshold
Severe Overvoltage Threshold
OCSET Reference Current
OC Threshold Offset
Current Imbalance Threshold
Undervoltage Threshold
(VDIFF/SOFT)
LOGIC THRESHOLDS
VR_ON, DPRSLPVR and PGD_IN
Input Low
VR_ON, DPRSLPVR and PGD_IN
Input High
VID0-VID6, PSI#, DPRSTP# Input
Low
VID0-VID6, PSI#, DPRSTP# Input
High
PWM
PWM (PWM1-PWM3) Output Low
FCCM Output Low
PWM (PWM1-PWM3) and FCCM
Output High
PWM Tri-State Leakage
THERMAL MONITOR
NTC Source Current
Over-Temperature Threshold
VR_TT# Low Output Resistance
CLK_EN# OUTPUT LEVELS
CLK_EN# High Output Voltage
CLK_EN# Low Output Voltage
V
OH
V
OL
3V3 = 3.3V, I = -4mA
I = 4mA
2.9
3.1
0.26
0.4
V
V
R
TT
NTC = 1.3V
V (NTC) falling
I = 20mA
53
1.165
60
1.18
6.5
67
1.2
9
μA
V
Ω
V
OL(5.0V)
V
OL_FCCM
V
OH(5.0V)
Sinking 5mA
Sinking 3mA
Sourcing 5mA
PWM = 2.5V
3.5
-1
1
1.0
1.0
V
V
V
μA
V
IL(3.3V)
V
IH(3.3V)
V
IL(1.0V)
V
IH(1.0V)
0.7
2.3
0.3
1.0
V
V
V
V
UV
f
V
OL
I
OH
tpgd
OV
H
OV
HS
I
PGOOD
= 4mA
PGOOD = 3.3V
CLK_ENABLE# LOW to PGOOD HIGH
VO rising above setpoint for >1ms
VO rising for >2µs
I(Rbias) = 10µA
DROOP rising above OCSET for >150μs
One ISEN above another ISEN for >1.2ms
VO falling below setpoint for >1.2ms
-355
-1
5.5
160
1.675
9.8
-2
9
-295
-235
6.8
200
1.7
10
0.26
0.4
1
8.1
240
1.725
10.2
4
V
μA
ms
mV
V
μA
mV
mV
mV
5
FN9162.1
January 3, 2006
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