®
Understanding Intersil Hot Plug Devices
Technical Brief
April 18, 2006
TB457.0
Authors: Eric Josefson and Sean Barr
Overview
Hot Plug controllers have two primary responsibilities,
control inrush currents during turn-on and control load
currents to a safe pre-determined level in the event of a high
current fault/short during static operation.
Devices Under Observation
• ISL6116 (+5V)
• ISL6116 (-12V)
• ISL6116 (-48V)
• ISL6115 (+12V)
• HIP1012A (+5V and +3.3V)
• ISL6173 (+3.3V and +2.5V)
• ISL6111(+12V, -12V, +3.3V, +5V)
• ISL6118 (+5V x2)
• Setting the Overcurrent Trip Point
C
TIM
DISCHARGED
R
ISET
IS USED TO SET THE
DEVICE’S OVERCURRENT
THRESHOLD POINT*
I
S
V
SENSE
> V
SET
?
NO
YES
CURRENT THROUGH R
ISENSE
GENERATES A VOLTAGE TO BE
COMPARED TO THRESHOLD
POINT DEFINED BY R
ISET
C
TIM
CHARGED
HAS TIMEOUT
OCCURRED?**
NO
YES
FAULT CONDITION
*See respective controller datasheet for equations to select R
ISET
**Timeout is proportional to CTIM and varies by controller
(see datasheets)
OVERCURRENT TRIP POINT OPERATION
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Technical Brief 457
ISL6116 (+5V)
Figures 1 and 2 show the ISL6116 in an ISL6115 high side
switch application eval board. Jumper JP1 is removed from
the original configuration so a +5V Power Source can be
applied to B2. +12V is needed to bias the IC and is applied
at B1. The overcurrent set point is 1.5A.
In Figure 3, notice the soft-start ramp up of GATE after
PWRON is initiated, thus allowing the gradual ramp up of
I
LOAD
. In Figure 4, starting up into a short is shown. Upon
PWRON being asserted, CTIM is immediately begins
charging. The nominal time-out period is CTIM x 93kΩ . An
overcurrent (OC) event occurs when the current through the
sense resistor exceeds the user programmed OC threshold
(see data sheet). The controller enters current regulation
(CR) and capacitor CTIM begins charging. The nominal
time-out period is CTIM x 93kΩ. (see Figure 5A). A transient
event from 500mA to 1A occurs. PGOOD is pulled low due
to a temporary undervoltage condition occurring on +5V
OUT
,
but CTIM stays low as a true OC event never occurs (See
Figure 5B).
ISL6116 (+5V) Figures
+
B3
LOAD
B4
-
+5V
R2
1
R1
2
3
Q1
R3
C1
JP1
+12V
V
BIAS
B1
4
ISL6116
U1
8
7
6
5
D1
R4
DD1
3.3V
C2
D2
PGOOD
R5
PWRON
C3
B5
+5V
V+ B2
FIGURE 1. EVAL BOARD SCHEMATIC
FIGURE 2. EVAL BOARD PICTURE
I
CR
= 1.5A
Ch3 PGOOD
I
CR
= 1.5A
Ch2 CTIM
Ch2 PWRON
Ch4 I
LOAD
Ch1 GATE
Ch1 GATE
Ch4 I
LOAD
Ch3 PGOOD
FIGURE 3. TURN ON VIA PWRON INTO NOMINAL LOAD
FIGURE 4. TURN ON VIA PWRON INTO SHORT
2
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April 18, 2006
Technical Brief 457
ISL6116 (+5V) Figures
(Continued)
I
CR
= 1.5A
Ch3PGOOD
Ch3 PGOOD
Ch1 +5V
OUT
Ch4 I
OUT
Ch1 GATE
Ch4 I
LOAD
Ch2 CTIM
Ch2CTIM
FIGURE 5A. RESPONSE TO OC DURING OPERATION
FIGURE 5.
FIGURE 5B. RESPONSE TO FALSE FAULT EVENT
ISL6116 (-12V)
Figures 6 and 7 show the ISL6116 reconfigured for -12V low
side switch application. The following components were
removed: RG1, R6 & R11. C2 was added (0.047µf 0805
size). In Figure 8, notice that GATE is 0V to fully enhance the
FET because of -12V operation. Also note that PGOOD is
disabled due to low side configuration. Upon power up,
current regulation mode is entered and CTIM is immediately
begins charging. The nominal time-out period is CTIM x
93kΩ, and again PGOOD is disabled (see Figure 9). An OC
event occurs when the current through the sense resistor
exceeds the user programmed OC threshold (see data
sheet). The controller enters CR mode and capacitor CTIM
begins charging. The nominal time-out period is CTIM x
93kΩ (see Figure 10).
ISL6116 (-12V) Figures
HI J2
GND
J1
+VBUS
LOAD
C1
R7
R2
J3 LO
Q2
R1
-12V APPL.
J4
-VBUS
-12V*
REMOVE:
RG1, R6, R11
ADD C2
1
4
C3
ISL6116
U1
5
DD1
3.3V
6
7
R5
R9
OFF
0-5V
OT1
ON
8
3
2
LOGIN
TP9
R8
R10
C2
D2
FIGURE 6. ISL6116EVAL1 NEGATIVE VOLTAGE LOW SIDE
CONTROLLER
FIGURE 7. ISL6116 EVAL BOARD PICTURE
3
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April 18, 2006
Technical Brief 457
ISL6116 (-12V) Figures
(Continued)
I
CR
= 2.4A
Ch4 I
LOAD
I
CR
= 2.4A
Ch1 GATE
Ch1 GATE
Ch4 I
LOAD
Ch2 CTIM
Ch3 PGOOD
Ch2 CTIM/Ch3 PGOOD
FIGURE 8. TURN ON INTO NOMINAL LOAD
FIGURE 9. TURN ON INTO OVERCURRENT
I
CR
= 2.4A
Ch4 I
LOAD
Ch1 GATE
Ch2 CTIM
FIGURE 10. RESPONSE TO OC DURING OPERATION
4
TB457.0
April 18, 2006
Technical Brief 457
ISL6116 (-48V)
Figure 11 and 12 show the ISL6116 in -48V Low Side Switch
Application. The eval board uses a HIP5600 to bias the
ISL6116 12V higher than the -48V. Note C2 was intentionally
left empty. Tests were done at -36V to keep the power
dissipated to the load low. Results would be essentially the
same at -48V.
In Figure 13, notice soft-start ramp up of GATE upon LOGIN
is being driven low. Keep in mind that PGOOD is disabled in
low side applications. Upon an OC at turn on, GATE begins
to soft-start, then attempts to regulate, then is shut down
(see Figure 14). Note CTIM’s behavior due to the eval board
setup (C2 DNP).
In Figure 15, the load is switched from an open to 2Ω. The
controller immediately pulls GATE down, CTIM up, and the
load is isolated. When LOGIN is forced high, the controller
shuts down (see Figure 16).
ISL6116 (-48V) Figures
HI J2
GND
J1
+VBUS
C1
R7
R2
LOAD
J3 LO
Q2
R1
J4
-VBUS
-48V
C2 = EMPTY
1
4
3
2
C3
ISL6116
U1
5
6
7
8
R
G
1
R6
R11
DD1
3.3V
R5
LOGIN
TP9
R8
R10
C2
D2
R9
OFF
0-5V
OT1
ON
FIGURE 11. ISL6116 EVAL BOARD SCHEMATIC
FIGURE 12. ISL6116 EVAL BOARD PICTURE
I
CR
= 2.4A
I
CR
= 2.4A
Ch2 GATE
Ch1 LOGIN
Ch1 LOGIN
Ch2 GATE
Ch3 CTIM
Ch4 I
LOAD
Ch4 I
LOAD
Ch3 CTIM
FIGURE 13. TURN ON VIA LOGIN
FIGURE 14. TURN ON INTO OC
5
TB457.0
April 18, 2006
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