ISL59444
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FN7451
Rev 3.00
August 16, 2012
1GHz, 4x1 Multiplexing Amplifier with Synchronous Controls
The ISL59444 is a single-output 4:1 MUX-amp. The MUX-amp
has a fixed gain of 1 and a 1GHz bandwidth. The ISL59444 is
ideal for professional video switching, HDTV, computer display
routing, and other high performance applications.
The device contains logic inputs for channel selection (S0,
S1), latch control signals (LE1, LE2), and a three-state output
control (HIZ) for individual selection of MUX amps that share
a common video output line. All logic inputs have pull-downs
to ground and may be left floating.
TABLE 1. TRUTH TABLE
LE1/LE2
0
0
0
0
X
HIZ
0
0
0
0
1
S1
0
0
1
1
X
S0
0
1
0
1
X
OUT
IN0
IN1
IN2
IN3
HiZ
Features
• 1GHz (-3dB) Bandwidth (V
OUT
= 200mV
P-P
)
• 220MHz (-3dB) Bandwidth (V
OUT
= 2V
P-P
)
• Slew Rate (R
L
= 500Ω
V
OUT
= 4V) . . . . . . . . . . . . . . . .1515V/µs
• Slew Rate (R
L
= 500Ω
V
OUT
= 5V) . . . . . . . . . . . . . . . .1155V/µs
• High Speed Three-State Output (HIZ)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
•
•
•
•
•
•
•
•
HDTV/DTV Analog Inputs
Video Projectors
Computer Monitors
Set-top Boxes
Security Video
Broadcast Video Equipment
RGB Video Distribution Systems
RF Switching and Routing
EN0
EN1
S0
S1
HIZ
EN3
LE1
LE2
100kΩ
DECODE
EN2
D
L
Q
C
D
L
Q
C
D
L
Q
C
D
L
Q
C
D
L
Q
C
D
L
Q
C
D
L
Q
C
D
L
Q
C
IN0
IN1
IN2
LE2
IN3
S0, S1, HIZ
OUT
CHX
CHX
CHY
CHZ
CHY
CHX
CHX
CHZ
CHZ
OUT
LE1
100kΩ
FIGURE 1. FUNCTIONAL DIAGRAM
FIGURE 2. TIMING DIAGRAM
FN7451 Rev 3.00
August 16, 2012
Page 1 of 13
ISL59444
Pin Configuration
ISL59444 (16 LD SO)
TOP VIEW
IN0 1
NIC 2
IN1 3
GND 4
IN2 5
NIC 6
IN3 7
NIC 8
16 V+
15 S0
14 S1
13 HIZ
12 OUT
11 LE2
10 LE1
9 V-
Pin Descriptions
PIN NUMBER
1
2, 6, 8
3
4
5
7
9
10
PIN NAME
IN0
NIC
IN1
GND
IN2
IN3
V-
LE1
Circuit 1
Circuit 4
Circuit 1
Circuit 1
Circuit 4
Circuit 2
EQUIVALENT
CIRCUIT
Circuit 1
Input for channel 0
Not Internally Connected; it is recommended this pin be tied to ground to minimize
crosstalk.
Input for channel 1
Ground pin
Input for channel 2
Input for channel 3
Negative Power Supply
Synchronized channel switching: When LE1 is low, the master control latch loads the
next switching address. The Mux Amp is configured for this address when LE2 goes low.
Synchronized operation results when LE2 is the inverse of LE1. Channel selection is
asynchronous (changes with any control signal change) if both LE1 and LE2 are
both low.
Synchronized channel switching: When LE2 is low, the newly selected channel, stored
in the master latch via LE1 is selected. Synchronized operation results when LE2 is the
inverse of LE1. Channel selection is asynchronous (changes with any control signal
change) if both LE1 and LE2 are both low.
Output
Output disable (active high); there are internal pull-down resistors, so the device will be
active with no connection; “HI” puts the output in high impedance state.
Channel selection pin MSB (binary logic code)
DESCRIPTION
11
LE2
Circuit 2
12
13
14
OUT
HIZ
S1
Circuit 3
Circuit 2
Circuit 2
FN7451 Rev 3.00
August 16, 2012
Page 2 of 13
ISL59444
Pin Descriptions
(Continued)
PIN NUMBER
15
16
PIN NAME
S0
V+
EQUIVALENT
CIRCUIT
Circuit 2
Circuit 4
V+
21k
IN
LOGICPIN
33k
+
-
GND.
DESCRIPTION
Channel selection pin LSB (binary logic code)
Positive power supply
V+
1.2V
V-
V-
CIRCUIT 1
CIRCUIT 2
V+
V+
OUT
GND
V-
V-
CAPACITIVELY
COUPLED
ESD CLAMP
CIRCUIT 3
CIRCUIT 4
Ordering Information
PART
NUMBER
(Notes 1, 2, 3)
ISL59444IBZ
ISL59444IBZ-T13
ISL59444IBZ-T7
NOTES:
1. Please refer to
TB347
for details on reel specifications.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL59444.
For more information on MSL please see tech brief
TB363.
4. SO16 (0.150”)
PART
MARKING
59444IBZ
59444IBZ
59444IBZ
TAPE &
REEL
-
7”
13”
PACKAGE
(Note 4)
16 Ld SO (Pb-free)
16 Ld SO (Pb-free)
16 Ld SO (Pb-free)
PKG.
DWG. #
MDP0027
MDP0027
MDP0027
FN7451 Rev 3.00
August 16, 2012
Page 3 of 13
ISL59444
Absolute Maximum Ratings
(T
A
= +25°C)
Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Digital and Analog Input Current (Note 5) . . . . . . . . . . . . . . . . . . . . . . 50mA
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . . . . 3kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Thermal Information
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figures 21 and 22
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figures 21 and 22
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
5. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
Electrical Specifications
PARAMETER
GENERAL
I
S
V+ = +5V, V- = -5V, GND = 0V, T
A
= +25°C, R
L
= 500Ω to GND, V
HIZ
= 0.8V, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
Supply Current (V
OUT
= 0V)
No load, V
HIZ
= 0.8V
No load, V
HIZ
= 2.0V
14.5
12.5
±3.2
±80
-2
18
16
±3.44
±120
9
-2.5
1.4
0.2
10
1.1
20
18
mA
mA
V
V
OUT
I
OUT
V
OS
Ib
R
out
Positive and Negative Output Swing
Output Current
Output Offset Voltage
Input Bias Current
Output Resistance
V
IN
= ±3.5V, R
L
= 500Ω
R
L
= 10Ω to GND
±180
20
-1
mA
mV
µA
MW
Ω
MΩ
pF
V
IN
= 0V
HIZ = logic high, (DC), A
V
= 1
HIZ = logic low, (DC), A
V
= 1
-5
R
IN
C
IN
A
CL
or A
V
I
TRI
LOGIC
V
H
V
L
I
IH
I
IL
t
LE
AC GENERAL
-3dB BW
Input Resistance
Input Capacitance
Voltage Gain
Output Current in Three-state
V
IN
= ±3.5V
V
IN
= ±1.5V, R
L
= 500Ω
V
OUT
= 0V
0.999
-35
1.001
6
1.003
+35
V/V
µA
Input High Voltage (Logic Inputs)
Input Low Voltage (Logic Inputs)
Input High Current (Logic Inputs)
Input Low Current (Logic Inputs)
LE1, LE2 Minimum Pulse Width
2
0.8
50
-10
-
4
150
5
-
V
V
µA
µA
ns
-3dB Bandwidth
V
OUT
= 200mV
P-P
, C
L
= 1.6pF
V
OUT
= 2V
P-P
, C
L
= 23.6pF,
R
S
= 25Ω
1.0
230
80
50
0.01
GHz
MHz
MHz
MHz
%
0.1dB BW
0.1dB Bandwidth
V
OUT
= 200mV
P-P
, C
L
= 1.6pF
V
OUT
= 2V
P-P
, C
L
= 23.6pF,
R
S
= 25Ω
dG
Differential Gain Error
NTSC-7, R
L
= 150
FN7451 Rev 3.00
August 16, 2012
Page 4 of 13
ISL59444
Electrical Specifications
PARAMETER
dP
+SR
-SR
PSRR
ISO
V+ = +5V, V- = -5V, GND = 0V, T
A
= +25°C, R
L
= 500Ω to GND, V
HIZ
= 0.8V, unless otherwise specified. (Continued)
DESCRIPTION
CONDITIONS
NTSC-7, R
L
= 150
25% to 75%, V
OUT
= 5V,
R
L
= 500Ω, C
L
= 23.6pF, R
S
= 25Ω
25% to 75%, V
OUT
= 5V,
R
L
= 500Ω, C
L
= 23.6pF, R
S
= 25Ω
DC, PSRR V+ and V- combined
V± = ±4.5V to ±5.5V
f = 10MHz, Ch-Ch X-Talk and Off
Isolation, C
L
= 1.6pF
-50
MIN
(Note 6)
TYP
0.02
1515
1155
-57
75
MAX
(Note 6)
UNIT
°
V/µs
V/µs
dB
dB
Differential Phase Error
Slew Rate
Slew Rate
Power Supply Rejection Ratio
Channel Isolation
SWITCHING CHARACTERISTICS
V
GLITCH
Channel-to-Channel Switching Glitch
HIZ Switching Glitch
t
SW-L-H
t
SW-H-L
TRANSIENT RESPONSE
tr, tf
Rise and Fall Time, 10% to 90%
V
OUT
= 200mV
P-P
, C
L
= 1.6pF
V
OUT
= 2V
P-P
, C
L
= 23.6pF,
R
S
= 25Ω
t
S
t
PLH
0.1% Settling Time
Propagation Delay - Low to High,
10% to 10%
V
OUT
= 2V
P-P
, C
L
= 23.6pF,
R
S
= 25Ω
V
OUT
= 200mV
P-P
, C
L
= 1.6pF
V
OUT
= 2V
P-P
, C
L
= 23.6pF,
R
S
= 25Ω
V
OUT
= 200mV
P-P
, C
L
= 1.6pF
V
OUT
= 2V
P-P
, C
L
= 23.6pF,
R
S
= 25Ω
V
OUT
= 200mV
P-P
, C
L
= 1.6pF
V
OUT
= 2V
P-P
, C
L
= 23.6pF,
R
S
= 25Ω
0.68
1.4
6.8
0.5
0.85
0.54
0.88
8.3
15.7
ns
ns
ns
ns
ns
ns
ns
%
%
Channel Switching Time Low to High
Channel Switching Time High to Low
V
IN
= 0V, C
L
= 23.6pF, R
S
= 25Ω
V
IN
= 0V, C
L
= 23.6pF, R
S
= 25Ω
1.2V logic threshold to 10%
movement of analog output
1.2V logic threshold to 10%
movement of analog output
38
175
32
29
mV
P-P
mV
P-P
ns
ns
t
PHL
Propagation Delay- High to Low,
10% to 10%
O
S
Overshoot
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN7451 Rev 3.00
August 16, 2012
Page 5 of 13
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