CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Integral Non-Linearity, INL
Differential Non-Linearity
Offset Error, V
OS
Offset Error Drift
Full Scale Error, FSE
Noise, e
N
AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, V
RHI
= +2.5V, V
RLO
= AGND = 0V, V
CM
= AGND,
PGIA Gain = 1, OSC
IN
= 10MHz, Bipolar Input Range Selected, f
N
= 10Hz
TEST CONDITIONS
MIN
TYP
0.0015
MAX
0.003
UNITS
End Point Line Method (Notes 3, 5, 6)
(Note 2)
(See Table 1)
V
INHI
= V
INLO
(Notes 3, 8)
V
INHI
- V
INLO
= +2.5V (Notes 3, 5, 8, 10)
(See Table 1)
V
CM
= 0V, V
INHI
= V
INLO
from -2V to +2V
Filter Notch = 10Hz, 25Hz, 50Hz (Note 2)
Filter Notch = 10Hz, 30Hz, 60Hz (Note 2)
-
%FS
LSB
-
V/
°C
-
-
dB
dB
dB
Conversions
No Missing codes to 20-Bits
-
-
-
-
-
120
120
-
-
1
-
-
70
-
-
2
-
-
-
-
-
-
-
4
Common Mode Rejection Ratio, CMRR
Normal Mode 50Hz Rejection
Normal Mode 60Hz Rejection
Step Response Settling Time
ANALOG INPUTS
Input Voltage Range
Input Voltage Range
Common Mode Input Range
Input Leakage Current, I
IN
Input Capacitance, C
IN
Reference Voltage Range, V
REF
(V
REF
= V
RHI
- V
RLO
)
Transducer Burn-Out Current, I
BO
CALIBRATION LIMITS
Positive Full Scale Calibration Limit
Negative Full Scale Calibration Limit
Offset Calibration Limit
Input Span
DIGITAL INPUTS
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Unipolar Mode (Note 9)
Bipolar Mode (Note 9)
(Note 2)
V
IN
= AV
DD
(Note 2)
0
- V
REF
AV
SS
-
-
2.5
-
-
-
-
-
5.0
-
200
V
REF
V
REF
AV
DD
1.0
-
5
-
V
V
V
nA
pF
V
nA
-
-
-
0.2(V
REF
/Gain)
(Note 11)
2.0
-
-
-
-
-
1.2(V
REF
/Gain)
1.2(V
REF
/Gain)
1.2(V
REF
/Gain)
2.4(V
REF
/Gain)
-
0.8
-
-
-
-
-
-
V
V
FN4138 Rev 8.00
June 1, 2006
Page 4 of 25
HI7191
Electrical Specifications
PARAMETER
Input Logic Current, I
I
Input Capacitance, C
IN
DIGITAL OUTPUTS
Output Logic High Voltage, V
OH
Output Logic Low Voltage, V
OL
Output Three-State Leakage Current,
I
OZ
Digital Output Capacitance, C
OUT
TIMING CHARACTERISTICS
SCLK Minimum Cycle Time, t
SCLK
SCLK Minimum Pulse Width, t
SCLKPW
CS to SCLK Precharge Time, t
PRE
DRDY Minimum High Pulse Width
Data Setup to SCLK Rising Edge
(Write), t
DSU
Data Hold from SCLK Rising Edge
(Write), t
DHLD
Data Read Access from Instruction Byte (Note 7)
Write, t
ACC
Read Bit Valid from SCLK Falling Edge,
t
DV
Last Data Transfer to Data Ready
Inactive, t
DRDY
RESET Low Pulse Width
SYNC Low Pulse Width
Oscillator Clock Frequency
Output Rise/Fall Time
Input Rise/Fall Time
POWER SUPPLY CHARACTERISTICS
IAV
DD
IAV
SS
IDV
DD
Power Dissipation, Active PD
A
Power Dissipation, Standby PD
S
PSRR
NOTES:
2. Parameter guaranteed by design or characterization, not production tested.
3. Applies to both bipolar and unipolar input ranges.
4. These errors can be removed by re-calibrating at the desired operating temperature.
5. Applies after system calibration.
6. Fully differential input signal source is used.
7. See Load Test Circuit, Figure 10, R1 = 10k, C
L
= 50pF.
8. 1 LSB = 298nV at 24 bits for a Full Scale Range of 5V.
9. V
REF
= V
RHI
- V
RLO.
10. These errors are on the order of the output noise shown in Table 1.
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