DATASHEET
CA3054
Dual Independent Differential Amp for Low Power Applications from DC to
120MHz
The CA3054 consists of two independent differential
amplifiers with associated constant current transistors on a
common monolithic substrate. The six NPN transistors which
comprise the amplifiers are general purpose devices which
exhibit low 1/f noise and a value of f
T
in excess of 300MHz.
These feature make the CA3054 useful from DC to 120MHz.
Bias and load resistors have been omitted to provide
maximum application flexibility.
The monolithic construction of the CA3054 provides close
electrical and thermal matching of the amplifiers. This
feature makes these devices particularly useful in dual
channel applications where matched performance of the two
channels is required.
FN388
Rev.6.00
Jan 13, 2017
Features
• Two Differential Amplifiers on a Common Substrate
• Independently Accessible Inputs and Outputs
• Maximum Input Offset Voltage. . . . . . . . . . . . . . . . .
5mV
• Temperature Range . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
•
Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Dual Sense Amplifiers
• Dual Schmitt Triggers
• Multifunction Combinations
- RF/Mixer/Oscillator; Converter/IF
Ordering Information
PART NUMBER
(BRAND)
CA3054M96
(3054)
CA3054MZ
(CA3054MZ)
CA3054MZ96
(CA3054MZ)
TEMP.
RANGE (°C)
0 to 85
0 to 85
0 to 85
PACKAGE
14 Ld SOIC
Tape and Reel
14 Ld SOIC
(Pb-free)
PKG.
DWG. #
M14.15
M14.15
• IF Amplifiers (Differential and/or Cascode)
• Product Detectors
• Doubly Balanced Modulators and Demodulators
• Balanced Quadrature Detectors
• Cascade Limiters
• Synchronous Detectors
• Pairs of Balanced Mixers
• Synthesizer Mixers
• Balanced (Push-Pull) Cascode Amplifiers
14 Ld SOIC Tape M14.15
and Reel (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinout
CA3054 (SOIC)
TOP VIEW
1
2
3
4
SUBSTRATE 5
6
7
Q
3
Q
4
Q
5
Q
6
Q
2
Q
1
14
13
12
11
10 NC
9
8
FN388 Rev.6.00
Jan 13, 2017
Page 1 of 8
CA3054
Absolute Maximum Ratings
T
A
= 25°C
Collector-to-Emitter Voltage, V
CEO
. . . . . . . . . . . . . . . . . . . . . . 15V
Collector-to-Base Voltage, V
CBO
. . . . . . . . . . . . . . . . . . . . . . . . 20V
Collector-to-Substrate Voltage, V
CIO
(Note 1). . . . . . . . . . . . . . 20V
Emitter-to-Base Voltage, V
EBO
. . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Collector Current, I
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Thermal Information
Thermal Resistance (Typical, Note 2)
JA
(°C/W)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . . 175°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(Lead Tips Only)
Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The collector of each transistor of the CA3054 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage
which is more negative than any collector voltage in order to maintain isolation between transistors and provide for normal transistor action. The
substrate should be maintained at signal (AC) ground by means of a suitable grounding capacitor, to avoid undesired coupling between transistors.
2.
JA
is measured with the component mounted on an evaluation PC board in free air.
Maximum Voltage Ratings
The following chart gives the range of voltages which can be applied to the terminals listed vertically with respect to the termi-
nals listed horizontally. For example, the voltage range of the vertical Terminal 2 with respect to Terminal 4 is +15V to -5V.
(NOTE 4)
TERM
NO.
13
13
14
1
2
3
4
6
7
8
9
11
12
5
Maximum
Current Ratings
(NOTE 4)
TERM
I
IN
NO.
mA
13
14
1
2
3
4
6
7
8
9
11
12
5
50
50
5
5
0.1
5
50
50
5
5
0.1
I
OUT
mA
0.1
0.1
0.1
0.1
0.1
50
0.1
0.1
0.1
0.1
0.1
50
14
0, -20
1
Note 3
2
+5, -5
3
4
6
7
8
9
11
12
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
-1, -5
5
Note 3
+20, 0
+20, 0
Note 3
Note 3
Note 3
+20, 0
+20, 0
Note 3
Note 3
Ref.
Sub-
strate
Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3
Note 3 Note 3 Note 3 +20, 0 Note 3 Note 3 Note 3 Note 3 Note 3
+20, 0 Note 3 +20, 0 Note 3 Note 3 Note 3 Note 3 Note 3
Note 3 +15, -5 Note 3 Note 3 Note 3 Note 3 Note 3
+1, -5
Note 3 Note 3 Note 3 Note 3 Note 3
Note 3 Note 3 Note 3 Note 3 Note 3
0, -20
Note 3
+5, -5
Note 3 Note 3 Note 3
+20, 0 Note 3
Note 3 +15, -5 Note 3
Note 3 +15, -5 Note 3
NOTES:
3. Voltages are not normally applied between these terminals. Voltages appearing between these terminals will be safe
if the specified limits between all other terminals are not exceeded.
4. Terminal No. 10 of CA3054 is not used.
Electrical Specifications
T
A
= 25°C
PARAMETER
DC CHARACTERISTICS
Input Offset Voltage (Figure 8)
Input Offset Current (Figure 9)
Input Bias Current (Figure 5)
Quiescent Operating Current Ratio
(Figure 5)
Temperature Coefficient Magnitude of
Input Offset Voltage (Figure 7)
SYMBOL
V
IO
I
IO
I
I
I C(Q1)
I C(Q5)
-----------------
or
-----------------
-
-
I C(Q2)
I C(Q6)
V
IO
----------------
-
T
TEST CONDITIONS
V
CB
= 3V, I
E(Q3)
= I
E(Q4)
= 2mA
V
CB
= 3V, I
E(Q3)
= I
E(Q4)
= 2mA
V
CB
= 3V, I
E(Q3)
= I
E(Q4)
= 2mA
V
CB
= 3V, I
E(Q3)
= I
E(Q4)
= 2mA
MIN
-
-
-
-
TYP
0.45
0.3
10
0.98 to
1.02
1.1
MAX
5
2
24
-
UNIT
mV
A
A
-
For Each Differential Amplifier
V
CB
= 3V, I
E(Q3)
= I
E(Q4)
= 2mA
-
-
V/°C
FN388 Rev.6.00
Jan 13, 2017
Page 2 of 8
CA3054
Electrical Specifications
T
A
= 25°C
(Continued)
PARAMETER
FOR EACH TRANSISTOR
DC Forward Base-to-Emitter Voltage
(Figure 8)
V
BE
V
CB
= 3V
I
C
= 50A
I
C
= 1mA
I
C
= 3mA
I
C
= 10mA
Temperature Coefficient of Base-to-Emitter
Voltage (Figure 6)
Collector Cutoff Current (Figure 4)
Collector-to-Emitter Breakdown Voltage
Collector-to-Base Breakdown Voltage
Collector-to-Substrate Breakdown
Voltage
Emitter-to-Base Breakdown Voltage
DYNAMIC CHARACTERISTICS
Common Mode Rejection Ratio for each
Amplifier (Figures 1, 10)
AGC Range, One Stage (Figures 2, 11)
Voltage Gain, Single Stage Double-Ended
Output (Figures 2, 11)
AGC Range, Two Stage (Figures 3, 12)
Voltage Gain, Two Stage Double-Ended Output
(Figures 3, 12)
Low Frequency, Small Signal Equivalent Circuit
Characteristics (For Single Transistor)
Forward Current Transfer Ratio (Figure 13)
Short Circuit Input Impedance (Figure 13)
Open Circuit Output Impedance
(Figure 13)
Open Circuit Reverse Voltage Transfer
Ratio (Figure 13)
1/f Noise Figure for Single Transistor
Gain Bandwidth Product for Single
Transistor (Figure 14)
Admittance Characteristics; Differential
Circuit Configuration (For Each Amplifier)
Forward Transfer Admittance (Figure 15)
Input Admittance (Figure 16)
Output Admittance (Figure 17)
Reverse Transfer Admittance (Figure 18)
Y
21
Y
11
Y
22
Y
12
V
CB
= 3V, f = 1MHz
Each Collector I
C
1.25mA
V
CB
= 3V, f = 1MHz
Each Collector I
C
1.25mA
V
CB
= 3V, f = 1MHz
Each Collector I
C
1.25mA
V
CB
= 3V, f = 1MHz
Each Collector I
C
1.25mA
-
-
-
-
-20 + j0
0.22 +
j0.1
0.01 +
j0
-0.003
+ j0
-
-
-
-
mS
mS
mS
mS
h
FE
h
IE
h
OE
h
RE
NF
f
T
f = 1kHz, V
CE
= 3V, I
C
= 1mA
f = 1kHz, V
CE
= 3V, I
C
= 1mA
f = 1kHz, V
CE
= 3V, I
C
= 1mA
f = 1kHz, V
CE
= 3V, I
C
= 1mA
f = 1kHz, V
CE
= 3V
V
CE
= 3V, I
C
= 3mA
-
-
-
-
-
-
110
3.5
15.6
1.8 x
10
-4
3.25
550
-
-
-
-
-
-
-
k
S
-
dB
MHz
CMRR
AGC
A
AGC
A
V
CC
= 12V, V
EE
= -6V,
V
X
= -3.3V, f = 1kHz
V
CC
= 12V, V
EE
= -6V,
V
X
= -3.3V, f = 1kHz
V
CC
= 12V, V
EE
= -6V,
V
X
= -3.3V, f = 1kHz
V
CC
= 12V, V
EE
= -6V,
V
X
= -3.3V, f = 1kHz
V
CC
= 12V, V
EE
= -6V,
V
X
= -3.3V, f = 1kHz
-
-
-
-
-
100
75
32
105
60
-
-
-
-
-
dB
dB
dB
dB
dB
V
BE
---------------
-
T
I
CBO
V
(BR)CEO
V
(BR)CBO
V
(BR)CIO
V
(BR)EBO
V
CB
= 3V, I
C
= 1mA
-
-
-
-
-
0.630
0.715
0.750
0.800
-1.9
0.700
0.800
0.850
0.900
-
V
V
V
V
V/°C
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
CB
= 10V, I
E
= 0
I
C
= 1mA, I
B
= 0
I
C
= 10A, I
E
= 0
I
C
= 10A, I
CI
= 0
I
E
= 10A, I
C
= 0
-
15
20
20
5
0.002
24
60
60
7
100
-
-
-
-
nA
V
V
V
V
FN388 Rev.6.00
Jan 13, 2017
Page 3 of 8
CA3054
Electrical Specifications
T
A
= 25°C
(Continued)
PARAMETER
Admittance Characteristics; Cascode Circuit Con-
figuration (For Each Amplifier)
Forward Transfer Admittance (Figure 19)
Input Admittance (Figure 20)
Output Admittance (Figure 21)
Reverse Transfer Admittance (Figure 22)
Noise Figure
Y
21
Y
11
Y
22
Y
12
NF
V
CB
= 3V, f = 1MHz
Total Stage I
C
2.5 mA
V
CB
= 3V, f = 1MHz
Total Stage I
C
2.5 mA
V
CB
= 3V, f = 1MHz
Total Stage I
C
2.5 mA
V
CB
= 3V, f = 1MHz
Total Stage I
C
2.5 mA
f = 100MHz
-
-
-
-
-
68 - j0
0.55 +
j0
0+
j0.02
0.004 -
j0.005
8
-
-
-
-
-
mS
mS
mS
S
dB
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Test Circuits
V
X
V
CC
= +12V
V
X
V
CC
= +12V
1k
V
IN
= 0.3V
RMS
10F
9
ICUT
SIGNAL
SOURCE
6
8
0.5k
0.5k
12
1k
11
7
0.1F
V
IN
= 10mV
RMS
10F
9
V
OUT
SIGNAL
SOURCE
1k
11
1k
7
ICUT
6
8
1k
0.5k
12
1k
0.1F
V
OUT
0.1F
V
EE
= -6V
V
CC
= +12V
0.1F
V
EE
= -6V
V
CC
= +12V
FIGURE 1. COMMON MODE REJECTION RATIO TEST SETUP
FIGURE 2. SINGLE STAGE VOLTAGE GAIN TEST SETUP
1F
1k
V
IN
= 1mV
RMS
10F
9
SIGNAL
SOURCE
1k
1k
6
3
11
V
X
1k
1F
13
ICUT
2
7
1
V
CC
= +12V
1k
1k
0.5k
0.1F
4
V
OUT
12
0.1F
V
EE
= -6V
8
14
1k
1k
V
CC
= +12V
0.5k
FIGURE 3. TWO STAGE VOLTAGE GAIN TEST SETUP
FN388 Rev.6.00
Jan 13, 2017
Page 4 of 8
CA3054
Typical Performance Curves
COLLECTOR CUTOFF CURRENT (nA)
10
2
I
E
= 0
V
CB
= 15V
V
CB
= 10V
V
CB
= 5V
INPUT BIAS CURRENT (A)
10
1
10
-1
10
-2
10
-3
10
-4
0
25
50
75
100
TEMPERATURE (°C) (NOTE)
125
100
V
CB
= 3V
T
A
= 25°C
10.0
1.0
0.1
1.0
COLLECTOR CURRENT (mA)
10
NOTE: For CA3054 use data from 0°C to 85°C only.
FIGURE 4. COLLECTOR-TO-BASE CUTOFF CURRENT vs
TEMPERATURE FOR EACH TRANSISTOR
FIGURE 5. INPUT BIAS CURRENT vs COLLECTOR CURRENT
FOR EACH TRANSISTOR
5
V
CB
= 3V
4
OFFSET VOLTAGE (mV)
3
2
0.75
0.50
0.25
25
50
75
100
125
0
-75
I
E
= 0.1mA
I
E
= 1mA
I
E
= 10mA
BASE-TO-EMITTER VOLTAGE (V)
V
CB
= 3V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
-75
I
E
= 3mA
I
E
= 1mA
I
E
= 0.5mA
-50
-25
0
-50
-25
0
25
50
75
100
125
TEMPERATURE (°C) (NOTE)
TEMPERATURE (°C) (NOTE)
NOTE: For CA3054 use data from 0°C to 85°C only.
FIGURE 6. BASE-TO-EMITTER VOLTAGE FOR EACH
TRANSISTOR vs TEMPERATURE
NOTE: For CA3054 use data from 0°C to 85°C only.
FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE FOR
DIFFERENTIAL PAIRS
0.8
BASE-TO-EMITTER VOLTAGE (V)
INPUT OFFSET VOLTAGE Q
1
AND Q
2
(mV)
V
CB
= 3V
T
A
= 25°C
4
10
INPUT OFFSET CURRENT (A)
V
CB
= 3V
T
A
= 25°C
0.7
V
BE
0.6
3
1.0
2
0.1
0.5
V
IO
= |V
BE1
- V
BE2
|
0.4
0.01
1
0
0.1
1.0
EMITTER CURRENT (mA)
10
0.01
0.01
0.1
1.0
10
COLLECTOR CURRENT (mA)
FIGURE 8. STATIC BASE-TO-EMITTER VOLTAGE AND INPUT
OFFSET VOLTAGE FOR DIFFERENTIAL PAIRS vs
EMITTER CURRENT
FIGURE 9. INPUT OFFSET CURRENT FOR MATCHED
DIFFERENTIAL PAIRS vs COLLECTOR CURRENT
FN388 Rev.6.00
Jan 13, 2017
Page 5 of 8
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